1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/uio_driver.h> 17 #include <linux/sh_cmt.h> 18 #include <asm/clock.h> 19 20 static struct resource iic_resources[] = { 21 [0] = { 22 .name = "IIC", 23 .start = 0x04470000, 24 .end = 0x04470017, 25 .flags = IORESOURCE_MEM, 26 }, 27 [1] = { 28 .start = 96, 29 .end = 99, 30 .flags = IORESOURCE_IRQ, 31 }, 32 }; 33 34 static struct platform_device iic_device = { 35 .name = "i2c-sh_mobile", 36 .id = 0, /* "i2c0" clock */ 37 .num_resources = ARRAY_SIZE(iic_resources), 38 .resource = iic_resources, 39 }; 40 41 static struct resource usb_host_resources[] = { 42 [0] = { 43 .name = "r8a66597_hcd", 44 .start = 0xa4d80000, 45 .end = 0xa4d800ff, 46 .flags = IORESOURCE_MEM, 47 }, 48 [1] = { 49 .name = "r8a66597_hcd", 50 .start = 65, 51 .end = 65, 52 .flags = IORESOURCE_IRQ, 53 }, 54 }; 55 56 static struct platform_device usb_host_device = { 57 .name = "r8a66597_hcd", 58 .id = -1, 59 .dev = { 60 .dma_mask = NULL, 61 .coherent_dma_mask = 0xffffffff, 62 }, 63 .num_resources = ARRAY_SIZE(usb_host_resources), 64 .resource = usb_host_resources, 65 }; 66 67 static struct uio_info vpu_platform_data = { 68 .name = "VPU5", 69 .version = "0", 70 .irq = 60, 71 }; 72 73 static struct resource vpu_resources[] = { 74 [0] = { 75 .name = "VPU", 76 .start = 0xfe900000, 77 .end = 0xfe902807, 78 .flags = IORESOURCE_MEM, 79 }, 80 [1] = { 81 /* place holder for contiguous memory */ 82 }, 83 }; 84 85 static struct platform_device vpu_device = { 86 .name = "uio_pdrv_genirq", 87 .id = 0, 88 .dev = { 89 .platform_data = &vpu_platform_data, 90 }, 91 .resource = vpu_resources, 92 .num_resources = ARRAY_SIZE(vpu_resources), 93 }; 94 95 static struct uio_info veu0_platform_data = { 96 .name = "VEU", 97 .version = "0", 98 .irq = 54, 99 }; 100 101 static struct resource veu0_resources[] = { 102 [0] = { 103 .name = "VEU(1)", 104 .start = 0xfe920000, 105 .end = 0xfe9200b7, 106 .flags = IORESOURCE_MEM, 107 }, 108 [1] = { 109 /* place holder for contiguous memory */ 110 }, 111 }; 112 113 static struct platform_device veu0_device = { 114 .name = "uio_pdrv_genirq", 115 .id = 1, 116 .dev = { 117 .platform_data = &veu0_platform_data, 118 }, 119 .resource = veu0_resources, 120 .num_resources = ARRAY_SIZE(veu0_resources), 121 }; 122 123 static struct uio_info veu1_platform_data = { 124 .name = "VEU", 125 .version = "0", 126 .irq = 27, 127 }; 128 129 static struct resource veu1_resources[] = { 130 [0] = { 131 .name = "VEU(2)", 132 .start = 0xfe924000, 133 .end = 0xfe9240b7, 134 .flags = IORESOURCE_MEM, 135 }, 136 [1] = { 137 /* place holder for contiguous memory */ 138 }, 139 }; 140 141 static struct platform_device veu1_device = { 142 .name = "uio_pdrv_genirq", 143 .id = 2, 144 .dev = { 145 .platform_data = &veu1_platform_data, 146 }, 147 .resource = veu1_resources, 148 .num_resources = ARRAY_SIZE(veu1_resources), 149 }; 150 151 static struct sh_cmt_config cmt_platform_data = { 152 .name = "CMT", 153 .channel_offset = 0x60, 154 .timer_bit = 5, 155 .clk = "cmt0", 156 .clockevent_rating = 125, 157 .clocksource_rating = 200, 158 }; 159 160 static struct resource cmt_resources[] = { 161 [0] = { 162 .name = "CMT", 163 .start = 0x044a0060, 164 .end = 0x044a006b, 165 .flags = IORESOURCE_MEM, 166 }, 167 [1] = { 168 .start = 104, 169 .flags = IORESOURCE_IRQ, 170 }, 171 }; 172 173 static struct platform_device cmt_device = { 174 .name = "sh_cmt", 175 .id = 0, 176 .dev = { 177 .platform_data = &cmt_platform_data, 178 }, 179 .resource = cmt_resources, 180 .num_resources = ARRAY_SIZE(cmt_resources), 181 }; 182 183 static struct plat_sci_port sci_platform_data[] = { 184 { 185 .mapbase = 0xffe00000, 186 .flags = UPF_BOOT_AUTOCONF, 187 .type = PORT_SCIF, 188 .irqs = { 80, 80, 80, 80 }, 189 }, { 190 .flags = 0, 191 } 192 }; 193 194 static struct platform_device sci_device = { 195 .name = "sh-sci", 196 .id = -1, 197 .dev = { 198 .platform_data = sci_platform_data, 199 }, 200 }; 201 202 static struct platform_device *sh7366_devices[] __initdata = { 203 &cmt_device, 204 &iic_device, 205 &sci_device, 206 &usb_host_device, 207 &vpu_device, 208 &veu0_device, 209 &veu1_device, 210 }; 211 212 static int __init sh7366_devices_setup(void) 213 { 214 clk_always_enable("rsmem0"); /* RSMEM */ 215 clk_always_enable("xymem0"); /* XYMEM */ 216 clk_always_enable("veu1"); /* VEU-2 */ 217 clk_always_enable("veu0"); /* VEU-1 */ 218 clk_always_enable("vpu0"); /* VPU */ 219 220 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 221 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 222 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 223 224 return platform_add_devices(sh7366_devices, 225 ARRAY_SIZE(sh7366_devices)); 226 } 227 __initcall(sh7366_devices_setup); 228 229 enum { 230 UNUSED=0, 231 232 /* interrupt sources */ 233 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 234 ICB, 235 DMAC0, DMAC1, DMAC2, DMAC3, 236 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 237 MFI, VPU, USB, 238 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 239 DMAC4, DMAC5, DMAC_DADERR, 240 SCIF, SCIFA1, SCIFA2, 241 DENC, MSIOF, 242 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 243 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 244 SDHI0, SDHI1, SDHI2, SDHI3, 245 CMT, TSIF, SIU, 246 TMU0, TMU1, TMU2, 247 VEU2, LCDC, 248 249 /* interrupt groups */ 250 251 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 252 }; 253 254 static struct intc_vect vectors[] __initdata = { 255 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 256 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 257 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 258 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 259 INTC_VECT(ICB, 0x700), 260 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 261 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 262 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 263 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 264 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 265 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 266 INTC_VECT(MMC_MMC3I, 0xb40), 267 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 268 INTC_VECT(DMAC_DADERR, 0xbc0), 269 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 270 INTC_VECT(SCIFA2, 0xc40), 271 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 272 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 273 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 274 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 275 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 276 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 277 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 278 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 279 INTC_VECT(SIU, 0xf80), 280 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 281 INTC_VECT(TMU2, 0x440), 282 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 283 }; 284 285 static struct intc_group groups[] __initdata = { 286 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 287 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 288 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 289 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 290 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 291 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 292 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 293 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 294 }; 295 296 static struct intc_mask_reg mask_registers[] __initdata = { 297 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 298 { } }, 299 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 300 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 301 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 302 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 303 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 304 { 0, 0, 0, ICB } }, 305 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 306 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 307 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 308 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 309 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 310 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 311 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 312 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 313 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 314 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 315 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 316 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 317 { 0, 0, 0, CMT, 0, USB, } }, 318 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 319 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 320 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 321 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 322 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 323 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 324 }; 325 326 static struct intc_prio_reg prio_registers[] __initdata = { 327 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 328 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 329 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 330 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 331 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 332 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 333 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 334 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 335 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 336 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 337 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 338 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 339 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 340 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 341 }; 342 343 static struct intc_sense_reg sense_registers[] __initdata = { 344 { 0xa414001c, 16, 2, /* ICR1 */ 345 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 346 }; 347 348 static struct intc_mask_reg ack_registers[] __initdata = { 349 { 0xa4140024, 0, 8, /* INTREQ00 */ 350 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 351 }; 352 353 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 354 mask_registers, prio_registers, sense_registers, 355 ack_registers); 356 357 void __init plat_irq_setup(void) 358 { 359 register_intc_controller(&intc_desc); 360 } 361 362 void __init plat_mem_setup(void) 363 { 364 /* TODO: Register Node 1 */ 365 } 366