1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 17 static struct plat_sci_port sci_platform_data[] = { 18 { 19 .mapbase = 0xffe00000, 20 .flags = UPF_BOOT_AUTOCONF, 21 .type = PORT_SCIF, 22 .irqs = { 80, 80, 80, 80 }, 23 }, { 24 .flags = 0, 25 } 26 }; 27 28 static struct platform_device sci_device = { 29 .name = "sh-sci", 30 .id = -1, 31 .dev = { 32 .platform_data = sci_platform_data, 33 }, 34 }; 35 36 static struct platform_device *sh7366_devices[] __initdata = { 37 &sci_device, 38 }; 39 40 static int __init sh7366_devices_setup(void) 41 { 42 return platform_add_devices(sh7366_devices, 43 ARRAY_SIZE(sh7366_devices)); 44 } 45 __initcall(sh7366_devices_setup); 46 47 enum { 48 UNUSED=0, 49 50 /* interrupt sources */ 51 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 52 ICB, 53 DMAC0, DMAC1, DMAC2, DMAC3, 54 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 55 MFI, VPU, USB, 56 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 57 DMAC4, DMAC5, DMAC_DADERR, 58 SCIF, SCIFA1, SCIFA2, 59 DENC, MSIOF, 60 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 61 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 62 SDHI0, SDHI1, SDHI2, SDHI3, 63 CMT, TSIF, SIU, 64 TMU0, TMU1, TMU2, 65 VEU2, LCDC, 66 67 /* interrupt groups */ 68 69 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 70 }; 71 72 static struct intc_vect vectors[] __initdata = { 73 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 74 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 75 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 76 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 77 INTC_VECT(ICB, 0x700), 78 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 79 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 80 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 81 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 82 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 83 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 84 INTC_VECT(MMC_MMC3I, 0xb40), 85 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 86 INTC_VECT(DMAC_DADERR, 0xbc0), 87 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 88 INTC_VECT(SCIFA2, 0xc40), 89 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 90 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 91 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 92 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 93 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 94 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 95 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 96 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 97 INTC_VECT(SIU, 0xf80), 98 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 99 INTC_VECT(TMU2, 0x440), 100 INTC_VECT(VEU2, 0x580), INTC_VECT(LCDC, 0x580), 101 }; 102 103 static struct intc_group groups[] __initdata = { 104 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 105 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 106 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 107 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 108 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 109 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 110 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 111 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 112 }; 113 114 static struct intc_mask_reg mask_registers[] __initdata = { 115 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 116 { } }, 117 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 118 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 119 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 120 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 121 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 122 { 0, 0, 0, ICB } }, 123 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 124 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 125 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 126 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 127 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 128 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 129 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 130 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 131 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 132 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 133 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 134 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 135 { 0, 0, 0, CMT, 0, USB, } }, 136 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 137 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 138 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 139 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 140 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 141 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 142 }; 143 144 static struct intc_prio_reg prio_registers[] __initdata = { 145 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 146 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 147 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 148 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 149 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 150 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 151 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 152 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 153 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 154 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 155 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 156 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 157 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 158 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 159 }; 160 161 static struct intc_sense_reg sense_registers[] __initdata = { 162 { 0xa414001c, 16, 2, /* ICR1 */ 163 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 164 }; 165 166 static DECLARE_INTC_DESC(intc_desc, "sh7366", vectors, groups, 167 mask_registers, prio_registers, sense_registers); 168 169 void __init plat_irq_setup(void) 170 { 171 register_intc_controller(&intc_desc); 172 } 173 174 void __init plat_mem_setup(void) 175 { 176 /* TODO: Register Node 1 */ 177 } 178