1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/uio_driver.h> 17 #include <asm/clock.h> 18 19 static struct resource iic_resources[] = { 20 [0] = { 21 .name = "IIC", 22 .start = 0x04470000, 23 .end = 0x04470017, 24 .flags = IORESOURCE_MEM, 25 }, 26 [1] = { 27 .start = 96, 28 .end = 99, 29 .flags = IORESOURCE_IRQ, 30 }, 31 }; 32 33 static struct platform_device iic_device = { 34 .name = "i2c-sh_mobile", 35 .num_resources = ARRAY_SIZE(iic_resources), 36 .resource = iic_resources, 37 }; 38 39 static struct resource usb_host_resources[] = { 40 [0] = { 41 .name = "r8a66597_hcd", 42 .start = 0xa4d80000, 43 .end = 0xa4d800ff, 44 .flags = IORESOURCE_MEM, 45 }, 46 [1] = { 47 .name = "r8a66597_hcd", 48 .start = 65, 49 .end = 65, 50 .flags = IORESOURCE_IRQ, 51 }, 52 }; 53 54 static struct platform_device usb_host_device = { 55 .name = "r8a66597_hcd", 56 .id = -1, 57 .dev = { 58 .dma_mask = NULL, 59 .coherent_dma_mask = 0xffffffff, 60 }, 61 .num_resources = ARRAY_SIZE(usb_host_resources), 62 .resource = usb_host_resources, 63 }; 64 65 static struct uio_info vpu_platform_data = { 66 .name = "VPU5", 67 .version = "0", 68 .irq = 60, 69 }; 70 71 static struct resource vpu_resources[] = { 72 [0] = { 73 .name = "VPU", 74 .start = 0xfe900000, 75 .end = 0xfe902807, 76 .flags = IORESOURCE_MEM, 77 }, 78 [1] = { 79 /* place holder for contiguous memory */ 80 }, 81 }; 82 83 static struct platform_device vpu_device = { 84 .name = "uio_pdrv_genirq", 85 .id = 0, 86 .dev = { 87 .platform_data = &vpu_platform_data, 88 }, 89 .resource = vpu_resources, 90 .num_resources = ARRAY_SIZE(vpu_resources), 91 }; 92 93 static struct uio_info veu0_platform_data = { 94 .name = "VEU", 95 .version = "0", 96 .irq = 54, 97 }; 98 99 static struct resource veu0_resources[] = { 100 [0] = { 101 .name = "VEU(1)", 102 .start = 0xfe920000, 103 .end = 0xfe9200b7, 104 .flags = IORESOURCE_MEM, 105 }, 106 [1] = { 107 /* place holder for contiguous memory */ 108 }, 109 }; 110 111 static struct platform_device veu0_device = { 112 .name = "uio_pdrv_genirq", 113 .id = 1, 114 .dev = { 115 .platform_data = &veu0_platform_data, 116 }, 117 .resource = veu0_resources, 118 .num_resources = ARRAY_SIZE(veu0_resources), 119 }; 120 121 static struct uio_info veu1_platform_data = { 122 .name = "VEU", 123 .version = "0", 124 .irq = 27, 125 }; 126 127 static struct resource veu1_resources[] = { 128 [0] = { 129 .name = "VEU(2)", 130 .start = 0xfe924000, 131 .end = 0xfe9240b7, 132 .flags = IORESOURCE_MEM, 133 }, 134 [1] = { 135 /* place holder for contiguous memory */ 136 }, 137 }; 138 139 static struct platform_device veu1_device = { 140 .name = "uio_pdrv_genirq", 141 .id = 2, 142 .dev = { 143 .platform_data = &veu1_platform_data, 144 }, 145 .resource = veu1_resources, 146 .num_resources = ARRAY_SIZE(veu1_resources), 147 }; 148 149 static struct plat_sci_port sci_platform_data[] = { 150 { 151 .mapbase = 0xffe00000, 152 .flags = UPF_BOOT_AUTOCONF, 153 .type = PORT_SCIF, 154 .irqs = { 80, 80, 80, 80 }, 155 }, { 156 .flags = 0, 157 } 158 }; 159 160 static struct platform_device sci_device = { 161 .name = "sh-sci", 162 .id = -1, 163 .dev = { 164 .platform_data = sci_platform_data, 165 }, 166 }; 167 168 static struct platform_device *sh7366_devices[] __initdata = { 169 &iic_device, 170 &sci_device, 171 &usb_host_device, 172 &vpu_device, 173 &veu0_device, 174 &veu1_device, 175 }; 176 177 static int __init sh7366_devices_setup(void) 178 { 179 clk_always_enable("mstp031"); /* TLB */ 180 clk_always_enable("mstp030"); /* IC */ 181 clk_always_enable("mstp029"); /* OC */ 182 clk_always_enable("mstp028"); /* RSMEM */ 183 clk_always_enable("mstp026"); /* XYMEM */ 184 clk_always_enable("mstp023"); /* INTC3 */ 185 clk_always_enable("mstp022"); /* INTC */ 186 clk_always_enable("mstp020"); /* SuperHyway */ 187 clk_always_enable("mstp109"); /* I2C */ 188 clk_always_enable("mstp211"); /* USB */ 189 clk_always_enable("mstp207"); /* VEU-2 */ 190 clk_always_enable("mstp202"); /* VEU-1 */ 191 clk_always_enable("mstp201"); /* VPU */ 192 193 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 194 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 195 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 196 197 return platform_add_devices(sh7366_devices, 198 ARRAY_SIZE(sh7366_devices)); 199 } 200 __initcall(sh7366_devices_setup); 201 202 enum { 203 UNUSED=0, 204 205 /* interrupt sources */ 206 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 207 ICB, 208 DMAC0, DMAC1, DMAC2, DMAC3, 209 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 210 MFI, VPU, USB, 211 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 212 DMAC4, DMAC5, DMAC_DADERR, 213 SCIF, SCIFA1, SCIFA2, 214 DENC, MSIOF, 215 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 216 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 217 SDHI0, SDHI1, SDHI2, SDHI3, 218 CMT, TSIF, SIU, 219 TMU0, TMU1, TMU2, 220 VEU2, LCDC, 221 222 /* interrupt groups */ 223 224 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 225 }; 226 227 static struct intc_vect vectors[] __initdata = { 228 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 229 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 230 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 231 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 232 INTC_VECT(ICB, 0x700), 233 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 234 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 235 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 236 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 237 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 238 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 239 INTC_VECT(MMC_MMC3I, 0xb40), 240 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 241 INTC_VECT(DMAC_DADERR, 0xbc0), 242 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 243 INTC_VECT(SCIFA2, 0xc40), 244 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 245 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 246 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 247 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 248 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 249 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 250 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 251 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 252 INTC_VECT(SIU, 0xf80), 253 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 254 INTC_VECT(TMU2, 0x440), 255 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 256 }; 257 258 static struct intc_group groups[] __initdata = { 259 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 260 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 261 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 262 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 263 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 264 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 265 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 266 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 267 }; 268 269 static struct intc_mask_reg mask_registers[] __initdata = { 270 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 271 { } }, 272 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 273 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 274 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 275 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 276 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 277 { 0, 0, 0, ICB } }, 278 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 279 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 280 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 281 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 282 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 283 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 284 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 285 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 286 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 287 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 288 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 289 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 290 { 0, 0, 0, CMT, 0, USB, } }, 291 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 292 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 293 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 294 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 295 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 296 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 297 }; 298 299 static struct intc_prio_reg prio_registers[] __initdata = { 300 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 301 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 302 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 303 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 304 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 305 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 306 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 307 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 308 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 309 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 310 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 311 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 312 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 313 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 314 }; 315 316 static struct intc_sense_reg sense_registers[] __initdata = { 317 { 0xa414001c, 16, 2, /* ICR1 */ 318 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 319 }; 320 321 static struct intc_mask_reg ack_registers[] __initdata = { 322 { 0xa4140024, 0, 8, /* INTREQ00 */ 323 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 324 }; 325 326 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 327 mask_registers, prio_registers, sense_registers, 328 ack_registers); 329 330 void __init plat_irq_setup(void) 331 { 332 register_intc_controller(&intc_desc); 333 } 334 335 void __init plat_mem_setup(void) 336 { 337 /* TODO: Register Node 1 */ 338 } 339