1 /* 2 * SH7366 Setup 3 * 4 * Copyright (C) 2008 Renesas Solutions 5 * 6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/platform_device.h> 13 #include <linux/init.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/uio_driver.h> 17 #include <linux/sh_timer.h> 18 #include <asm/clock.h> 19 20 static struct resource iic_resources[] = { 21 [0] = { 22 .name = "IIC", 23 .start = 0x04470000, 24 .end = 0x04470017, 25 .flags = IORESOURCE_MEM, 26 }, 27 [1] = { 28 .start = 96, 29 .end = 99, 30 .flags = IORESOURCE_IRQ, 31 }, 32 }; 33 34 static struct platform_device iic_device = { 35 .name = "i2c-sh_mobile", 36 .id = 0, /* "i2c0" clock */ 37 .num_resources = ARRAY_SIZE(iic_resources), 38 .resource = iic_resources, 39 }; 40 41 static struct resource usb_host_resources[] = { 42 [0] = { 43 .name = "r8a66597_hcd", 44 .start = 0xa4d80000, 45 .end = 0xa4d800ff, 46 .flags = IORESOURCE_MEM, 47 }, 48 [1] = { 49 .name = "r8a66597_hcd", 50 .start = 65, 51 .end = 65, 52 .flags = IORESOURCE_IRQ, 53 }, 54 }; 55 56 static struct platform_device usb_host_device = { 57 .name = "r8a66597_hcd", 58 .id = -1, 59 .dev = { 60 .dma_mask = NULL, 61 .coherent_dma_mask = 0xffffffff, 62 }, 63 .num_resources = ARRAY_SIZE(usb_host_resources), 64 .resource = usb_host_resources, 65 }; 66 67 static struct uio_info vpu_platform_data = { 68 .name = "VPU5", 69 .version = "0", 70 .irq = 60, 71 }; 72 73 static struct resource vpu_resources[] = { 74 [0] = { 75 .name = "VPU", 76 .start = 0xfe900000, 77 .end = 0xfe902807, 78 .flags = IORESOURCE_MEM, 79 }, 80 [1] = { 81 /* place holder for contiguous memory */ 82 }, 83 }; 84 85 static struct platform_device vpu_device = { 86 .name = "uio_pdrv_genirq", 87 .id = 0, 88 .dev = { 89 .platform_data = &vpu_platform_data, 90 }, 91 .resource = vpu_resources, 92 .num_resources = ARRAY_SIZE(vpu_resources), 93 }; 94 95 static struct uio_info veu0_platform_data = { 96 .name = "VEU", 97 .version = "0", 98 .irq = 54, 99 }; 100 101 static struct resource veu0_resources[] = { 102 [0] = { 103 .name = "VEU(1)", 104 .start = 0xfe920000, 105 .end = 0xfe9200b7, 106 .flags = IORESOURCE_MEM, 107 }, 108 [1] = { 109 /* place holder for contiguous memory */ 110 }, 111 }; 112 113 static struct platform_device veu0_device = { 114 .name = "uio_pdrv_genirq", 115 .id = 1, 116 .dev = { 117 .platform_data = &veu0_platform_data, 118 }, 119 .resource = veu0_resources, 120 .num_resources = ARRAY_SIZE(veu0_resources), 121 }; 122 123 static struct uio_info veu1_platform_data = { 124 .name = "VEU", 125 .version = "0", 126 .irq = 27, 127 }; 128 129 static struct resource veu1_resources[] = { 130 [0] = { 131 .name = "VEU(2)", 132 .start = 0xfe924000, 133 .end = 0xfe9240b7, 134 .flags = IORESOURCE_MEM, 135 }, 136 [1] = { 137 /* place holder for contiguous memory */ 138 }, 139 }; 140 141 static struct platform_device veu1_device = { 142 .name = "uio_pdrv_genirq", 143 .id = 2, 144 .dev = { 145 .platform_data = &veu1_platform_data, 146 }, 147 .resource = veu1_resources, 148 .num_resources = ARRAY_SIZE(veu1_resources), 149 }; 150 151 static struct sh_timer_config cmt_platform_data = { 152 .name = "CMT", 153 .channel_offset = 0x60, 154 .timer_bit = 5, 155 .clk = "cmt0", 156 .clockevent_rating = 125, 157 .clocksource_rating = 200, 158 }; 159 160 static struct resource cmt_resources[] = { 161 [0] = { 162 .name = "CMT", 163 .start = 0x044a0060, 164 .end = 0x044a006b, 165 .flags = IORESOURCE_MEM, 166 }, 167 [1] = { 168 .start = 104, 169 .flags = IORESOURCE_IRQ, 170 }, 171 }; 172 173 static struct platform_device cmt_device = { 174 .name = "sh_cmt", 175 .id = 0, 176 .dev = { 177 .platform_data = &cmt_platform_data, 178 }, 179 .resource = cmt_resources, 180 .num_resources = ARRAY_SIZE(cmt_resources), 181 }; 182 183 static struct sh_timer_config tmu0_platform_data = { 184 .name = "TMU0", 185 .channel_offset = 0x04, 186 .timer_bit = 0, 187 .clk = "tmu0", 188 .clockevent_rating = 200, 189 }; 190 191 static struct resource tmu0_resources[] = { 192 [0] = { 193 .name = "TMU0", 194 .start = 0xffd80008, 195 .end = 0xffd80013, 196 .flags = IORESOURCE_MEM, 197 }, 198 [1] = { 199 .start = 16, 200 .flags = IORESOURCE_IRQ, 201 }, 202 }; 203 204 static struct platform_device tmu0_device = { 205 .name = "sh_tmu", 206 .id = 0, 207 .dev = { 208 .platform_data = &tmu0_platform_data, 209 }, 210 .resource = tmu0_resources, 211 .num_resources = ARRAY_SIZE(tmu0_resources), 212 }; 213 214 static struct sh_timer_config tmu1_platform_data = { 215 .name = "TMU1", 216 .channel_offset = 0x10, 217 .timer_bit = 1, 218 .clk = "tmu0", 219 .clocksource_rating = 200, 220 }; 221 222 static struct resource tmu1_resources[] = { 223 [0] = { 224 .name = "TMU1", 225 .start = 0xffd80014, 226 .end = 0xffd8001f, 227 .flags = IORESOURCE_MEM, 228 }, 229 [1] = { 230 .start = 17, 231 .flags = IORESOURCE_IRQ, 232 }, 233 }; 234 235 static struct platform_device tmu1_device = { 236 .name = "sh_tmu", 237 .id = 1, 238 .dev = { 239 .platform_data = &tmu1_platform_data, 240 }, 241 .resource = tmu1_resources, 242 .num_resources = ARRAY_SIZE(tmu1_resources), 243 }; 244 245 static struct sh_timer_config tmu2_platform_data = { 246 .name = "TMU2", 247 .channel_offset = 0x1c, 248 .timer_bit = 2, 249 .clk = "tmu0", 250 }; 251 252 static struct resource tmu2_resources[] = { 253 [0] = { 254 .name = "TMU2", 255 .start = 0xffd80020, 256 .end = 0xffd8002b, 257 .flags = IORESOURCE_MEM, 258 }, 259 [1] = { 260 .start = 18, 261 .flags = IORESOURCE_IRQ, 262 }, 263 }; 264 265 static struct platform_device tmu2_device = { 266 .name = "sh_tmu", 267 .id = 2, 268 .dev = { 269 .platform_data = &tmu2_platform_data, 270 }, 271 .resource = tmu2_resources, 272 .num_resources = ARRAY_SIZE(tmu2_resources), 273 }; 274 275 static struct plat_sci_port sci_platform_data[] = { 276 { 277 .mapbase = 0xffe00000, 278 .flags = UPF_BOOT_AUTOCONF, 279 .type = PORT_SCIF, 280 .irqs = { 80, 80, 80, 80 }, 281 .clk = "scif0", 282 }, { 283 .flags = 0, 284 } 285 }; 286 287 static struct platform_device sci_device = { 288 .name = "sh-sci", 289 .id = -1, 290 .dev = { 291 .platform_data = sci_platform_data, 292 }, 293 }; 294 295 static struct platform_device *sh7366_devices[] __initdata = { 296 &cmt_device, 297 &tmu0_device, 298 &tmu1_device, 299 &tmu2_device, 300 &iic_device, 301 &sci_device, 302 &usb_host_device, 303 &vpu_device, 304 &veu0_device, 305 &veu1_device, 306 }; 307 308 static int __init sh7366_devices_setup(void) 309 { 310 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 311 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 312 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 313 314 return platform_add_devices(sh7366_devices, 315 ARRAY_SIZE(sh7366_devices)); 316 } 317 __initcall(sh7366_devices_setup); 318 319 static struct platform_device *sh7366_early_devices[] __initdata = { 320 &cmt_device, 321 &tmu0_device, 322 &tmu1_device, 323 &tmu2_device, 324 }; 325 326 void __init plat_early_device_setup(void) 327 { 328 early_platform_add_devices(sh7366_early_devices, 329 ARRAY_SIZE(sh7366_early_devices)); 330 } 331 332 enum { 333 UNUSED=0, 334 335 /* interrupt sources */ 336 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 337 ICB, 338 DMAC0, DMAC1, DMAC2, DMAC3, 339 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 340 MFI, VPU, USB, 341 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I, 342 DMAC4, DMAC5, DMAC_DADERR, 343 SCIF, SCIFA1, SCIFA2, 344 DENC, MSIOF, 345 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 346 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 347 SDHI0, SDHI1, SDHI2, SDHI3, 348 CMT, TSIF, SIU, 349 TMU0, TMU1, TMU2, 350 VEU2, LCDC, 351 352 /* interrupt groups */ 353 354 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI, 355 }; 356 357 static struct intc_vect vectors[] __initdata = { 358 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 359 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 360 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 361 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 362 INTC_VECT(ICB, 0x700), 363 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 364 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 365 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 366 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 367 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20), 368 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20), 369 INTC_VECT(MMC_MMC3I, 0xb40), 370 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 371 INTC_VECT(DMAC_DADERR, 0xbc0), 372 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20), 373 INTC_VECT(SCIFA2, 0xc40), 374 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80), 375 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 376 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 377 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 378 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 379 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 380 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 381 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 382 INTC_VECT(SIU, 0xf80), 383 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 384 INTC_VECT(TMU2, 0x440), 385 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580), 386 }; 387 388 static struct intc_group groups[] __initdata = { 389 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 390 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 391 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I), 392 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 393 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 394 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 395 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 396 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 397 }; 398 399 static struct intc_mask_reg mask_registers[] __initdata = { 400 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 401 { } }, 402 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 403 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 404 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 405 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 406 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 407 { 0, 0, 0, ICB } }, 408 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 409 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } }, 410 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 411 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } }, 412 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 413 { 0, 0, 0, 0, 0, 0, 0, MSIOF } }, 414 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 415 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 416 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 417 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 418 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 419 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 420 { 0, 0, 0, CMT, 0, USB, } }, 421 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 422 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } }, 423 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 424 { 0, 0, 0, 0, 0, 0, 0, TSIF } }, 425 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 426 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 427 }; 428 429 static struct intc_prio_reg prio_registers[] __initdata = { 430 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 431 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } }, 432 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 433 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 434 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 435 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } }, 436 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } }, 437 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } }, 438 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } }, 439 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 440 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 441 { 0xa408002c, 0, 16, 4, /* IPRL */ { } }, 442 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 443 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 444 }; 445 446 static struct intc_sense_reg sense_registers[] __initdata = { 447 { 0xa414001c, 16, 2, /* ICR1 */ 448 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 449 }; 450 451 static struct intc_mask_reg ack_registers[] __initdata = { 452 { 0xa4140024, 0, 8, /* INTREQ00 */ 453 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 454 }; 455 456 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups, 457 mask_registers, prio_registers, sense_registers, 458 ack_registers); 459 460 void __init plat_irq_setup(void) 461 { 462 register_intc_controller(&intc_desc); 463 } 464 465 void __init plat_mem_setup(void) 466 { 467 /* TODO: Register Node 1 */ 468 } 469