1 /* 2 * SH7343 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/uio_driver.h> 15 #include <asm/clock.h> 16 17 static struct resource iic0_resources[] = { 18 [0] = { 19 .name = "IIC0", 20 .start = 0x04470000, 21 .end = 0x04470017, 22 .flags = IORESOURCE_MEM, 23 }, 24 [1] = { 25 .start = 96, 26 .end = 99, 27 .flags = IORESOURCE_IRQ, 28 }, 29 }; 30 31 static struct platform_device iic0_device = { 32 .name = "i2c-sh_mobile", 33 .num_resources = ARRAY_SIZE(iic0_resources), 34 .resource = iic0_resources, 35 }; 36 37 static struct resource iic1_resources[] = { 38 [0] = { 39 .name = "IIC1", 40 .start = 0x04750000, 41 .end = 0x04750017, 42 .flags = IORESOURCE_MEM, 43 }, 44 [1] = { 45 .start = 44, 46 .end = 47, 47 .flags = IORESOURCE_IRQ, 48 }, 49 }; 50 51 static struct platform_device iic1_device = { 52 .name = "i2c-sh_mobile", 53 .num_resources = ARRAY_SIZE(iic1_resources), 54 .resource = iic1_resources, 55 }; 56 57 static struct uio_info vpu_platform_data = { 58 .name = "VPU4", 59 .version = "0", 60 .irq = 60, 61 }; 62 63 static struct resource vpu_resources[] = { 64 [0] = { 65 .name = "VPU", 66 .start = 0xfe900000, 67 .end = 0xfe9022eb, 68 .flags = IORESOURCE_MEM, 69 }, 70 [1] = { 71 /* place holder for contiguous memory */ 72 }, 73 }; 74 75 static struct platform_device vpu_device = { 76 .name = "uio_pdrv_genirq", 77 .id = 0, 78 .dev = { 79 .platform_data = &vpu_platform_data, 80 }, 81 .resource = vpu_resources, 82 .num_resources = ARRAY_SIZE(vpu_resources), 83 }; 84 85 static struct uio_info veu_platform_data = { 86 .name = "VEU", 87 .version = "0", 88 .irq = 54, 89 }; 90 91 static struct resource veu_resources[] = { 92 [0] = { 93 .name = "VEU", 94 .start = 0xfe920000, 95 .end = 0xfe9200b7, 96 .flags = IORESOURCE_MEM, 97 }, 98 [1] = { 99 /* place holder for contiguous memory */ 100 }, 101 }; 102 103 static struct platform_device veu_device = { 104 .name = "uio_pdrv_genirq", 105 .id = 1, 106 .dev = { 107 .platform_data = &veu_platform_data, 108 }, 109 .resource = veu_resources, 110 .num_resources = ARRAY_SIZE(veu_resources), 111 }; 112 113 static struct plat_sci_port sci_platform_data[] = { 114 { 115 .mapbase = 0xffe00000, 116 .flags = UPF_BOOT_AUTOCONF, 117 .type = PORT_SCIF, 118 .irqs = { 80, 81, 83, 82 }, 119 }, { 120 .flags = 0, 121 } 122 }; 123 124 static struct platform_device sci_device = { 125 .name = "sh-sci", 126 .id = -1, 127 .dev = { 128 .platform_data = sci_platform_data, 129 }, 130 }; 131 132 static struct platform_device *sh7343_devices[] __initdata = { 133 &iic0_device, 134 &iic1_device, 135 &sci_device, 136 &vpu_device, 137 &veu_device, 138 }; 139 140 static int __init sh7343_devices_setup(void) 141 { 142 clk_always_enable("mstp031"); /* TLB */ 143 clk_always_enable("mstp030"); /* IC */ 144 clk_always_enable("mstp029"); /* OC */ 145 clk_always_enable("mstp028"); /* URAM */ 146 clk_always_enable("mstp026"); /* XYMEM */ 147 clk_always_enable("mstp023"); /* INTC3 */ 148 clk_always_enable("mstp022"); /* INTC */ 149 clk_always_enable("mstp020"); /* SuperHyway */ 150 clk_always_enable("mstp109"); /* I2C0 */ 151 clk_always_enable("mstp108"); /* I2C1 */ 152 clk_always_enable("mstp202"); /* VEU */ 153 clk_always_enable("mstp201"); /* VPU */ 154 155 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 156 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 157 158 return platform_add_devices(sh7343_devices, 159 ARRAY_SIZE(sh7343_devices)); 160 } 161 __initcall(sh7343_devices_setup); 162 163 enum { 164 UNUSED = 0, 165 166 /* interrupt sources */ 167 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 168 DMAC0, DMAC1, DMAC2, DMAC3, 169 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 170 MFI, VPU, TPU, Z3D4, USBI0, USBI1, 171 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, 172 DMAC4, DMAC5, DMAC_DADERR, 173 KEYSC, 174 SCIF, SCIF1, SCIF2, SCIF3, SCIF4, 175 SIOF0, SIOF1, SIO, 176 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 177 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 178 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 179 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 180 IRDA, 181 SDHI0, SDHI1, SDHI2, SDHI3, 182 CMT, TSIF, SIU, 183 TMU0, TMU1, TMU2, 184 JPU, LCDC, 185 186 /* interrupt groups */ 187 188 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, 189 }; 190 191 static struct intc_vect vectors[] __initdata = { 192 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 193 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 194 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 195 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 196 INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), 197 INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), 198 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 199 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 200 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 201 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 202 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), 203 INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), 204 INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), 205 INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), 206 INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), 207 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 208 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 209 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), 210 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), 211 INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), 212 INTC_VECT(SIO, 0xd00), 213 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 214 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 215 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 216 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 217 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 218 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 219 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 220 INTC_VECT(SIU, 0xf80), 221 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 222 INTC_VECT(TMU2, 0x440), 223 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 224 }; 225 226 static struct intc_group groups[] __initdata = { 227 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 228 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 229 INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), 230 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 231 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 232 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 233 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 234 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 235 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 236 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 237 INTC_GROUP(USB, USBI0, USBI1), 238 }; 239 240 static struct intc_mask_reg mask_registers[] __initdata = { 241 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 242 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 243 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 244 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 245 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 246 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 247 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 248 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 249 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 250 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, 251 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 252 { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, 253 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 254 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 255 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 256 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 257 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 258 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 259 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 260 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 261 { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, 262 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 263 { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, 264 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 265 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 266 }; 267 268 static struct intc_prio_reg prio_registers[] __initdata = { 269 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 270 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 271 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 272 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 273 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, 274 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, 275 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, 276 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, 277 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 278 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, 279 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 280 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 281 }; 282 283 static struct intc_sense_reg sense_registers[] __initdata = { 284 { 0xa414001c, 16, 2, /* ICR1 */ 285 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 286 }; 287 288 static struct intc_mask_reg ack_registers[] __initdata = { 289 { 0xa4140024, 0, 8, /* INTREQ00 */ 290 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 291 }; 292 293 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, 294 mask_registers, prio_registers, sense_registers, 295 ack_registers); 296 297 void __init plat_irq_setup(void) 298 { 299 register_intc_controller(&intc_desc); 300 } 301