1 /* 2 * SH7343 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/uio_driver.h> 15 #include <linux/sh_timer.h> 16 #include <asm/clock.h> 17 18 /* Serial */ 19 static struct plat_sci_port scif0_platform_data = { 20 .mapbase = 0xffe00000, 21 .flags = UPF_BOOT_AUTOCONF, 22 .type = PORT_SCIF, 23 .irqs = { 80, 80, 80, 80 }, 24 .clk = "scif0", 25 }; 26 27 static struct platform_device scif0_device = { 28 .name = "sh-sci", 29 .id = 0, 30 .dev = { 31 .platform_data = &scif0_platform_data, 32 }, 33 }; 34 35 static struct plat_sci_port scif1_platform_data = { 36 .mapbase = 0xffe10000, 37 .flags = UPF_BOOT_AUTOCONF, 38 .type = PORT_SCIF, 39 .irqs = { 81, 81, 81, 81 }, 40 .clk = "scif1", 41 }; 42 43 static struct platform_device scif1_device = { 44 .name = "sh-sci", 45 .id = 1, 46 .dev = { 47 .platform_data = &scif1_platform_data, 48 }, 49 }; 50 51 static struct plat_sci_port scif2_platform_data = { 52 .mapbase = 0xffe20000, 53 .flags = UPF_BOOT_AUTOCONF, 54 .type = PORT_SCIF, 55 .irqs = { 82, 82, 82, 82 }, 56 .clk = "scif2", 57 }; 58 59 static struct platform_device scif2_device = { 60 .name = "sh-sci", 61 .id = 2, 62 .dev = { 63 .platform_data = &scif2_platform_data, 64 }, 65 }; 66 67 static struct plat_sci_port scif3_platform_data = { 68 .mapbase = 0xffe30000, 69 .flags = UPF_BOOT_AUTOCONF, 70 .type = PORT_SCIF, 71 .irqs = { 83, 83, 83, 83 }, 72 .clk = "scif3", 73 }; 74 75 static struct platform_device scif3_device = { 76 .name = "sh-sci", 77 .id = 3, 78 .dev = { 79 .platform_data = &scif3_platform_data, 80 }, 81 }; 82 83 static struct resource iic0_resources[] = { 84 [0] = { 85 .name = "IIC0", 86 .start = 0x04470000, 87 .end = 0x04470017, 88 .flags = IORESOURCE_MEM, 89 }, 90 [1] = { 91 .start = 96, 92 .end = 99, 93 .flags = IORESOURCE_IRQ, 94 }, 95 }; 96 97 static struct platform_device iic0_device = { 98 .name = "i2c-sh_mobile", 99 .id = 0, /* "i2c0" clock */ 100 .num_resources = ARRAY_SIZE(iic0_resources), 101 .resource = iic0_resources, 102 }; 103 104 static struct resource iic1_resources[] = { 105 [0] = { 106 .name = "IIC1", 107 .start = 0x04750000, 108 .end = 0x04750017, 109 .flags = IORESOURCE_MEM, 110 }, 111 [1] = { 112 .start = 44, 113 .end = 47, 114 .flags = IORESOURCE_IRQ, 115 }, 116 }; 117 118 static struct platform_device iic1_device = { 119 .name = "i2c-sh_mobile", 120 .id = 1, /* "i2c1" clock */ 121 .num_resources = ARRAY_SIZE(iic1_resources), 122 .resource = iic1_resources, 123 }; 124 125 static struct uio_info vpu_platform_data = { 126 .name = "VPU4", 127 .version = "0", 128 .irq = 60, 129 }; 130 131 static struct resource vpu_resources[] = { 132 [0] = { 133 .name = "VPU", 134 .start = 0xfe900000, 135 .end = 0xfe9022eb, 136 .flags = IORESOURCE_MEM, 137 }, 138 [1] = { 139 /* place holder for contiguous memory */ 140 }, 141 }; 142 143 static struct platform_device vpu_device = { 144 .name = "uio_pdrv_genirq", 145 .id = 0, 146 .dev = { 147 .platform_data = &vpu_platform_data, 148 }, 149 .resource = vpu_resources, 150 .num_resources = ARRAY_SIZE(vpu_resources), 151 }; 152 153 static struct uio_info veu_platform_data = { 154 .name = "VEU", 155 .version = "0", 156 .irq = 54, 157 }; 158 159 static struct resource veu_resources[] = { 160 [0] = { 161 .name = "VEU", 162 .start = 0xfe920000, 163 .end = 0xfe9200b7, 164 .flags = IORESOURCE_MEM, 165 }, 166 [1] = { 167 /* place holder for contiguous memory */ 168 }, 169 }; 170 171 static struct platform_device veu_device = { 172 .name = "uio_pdrv_genirq", 173 .id = 1, 174 .dev = { 175 .platform_data = &veu_platform_data, 176 }, 177 .resource = veu_resources, 178 .num_resources = ARRAY_SIZE(veu_resources), 179 }; 180 181 static struct uio_info jpu_platform_data = { 182 .name = "JPU", 183 .version = "0", 184 .irq = 27, 185 }; 186 187 static struct resource jpu_resources[] = { 188 [0] = { 189 .name = "JPU", 190 .start = 0xfea00000, 191 .end = 0xfea102d3, 192 .flags = IORESOURCE_MEM, 193 }, 194 [1] = { 195 /* place holder for contiguous memory */ 196 }, 197 }; 198 199 static struct platform_device jpu_device = { 200 .name = "uio_pdrv_genirq", 201 .id = 2, 202 .dev = { 203 .platform_data = &jpu_platform_data, 204 }, 205 .resource = jpu_resources, 206 .num_resources = ARRAY_SIZE(jpu_resources), 207 }; 208 209 static struct sh_timer_config cmt_platform_data = { 210 .name = "CMT", 211 .channel_offset = 0x60, 212 .timer_bit = 5, 213 .clk = "cmt0", 214 .clockevent_rating = 125, 215 .clocksource_rating = 200, 216 }; 217 218 static struct resource cmt_resources[] = { 219 [0] = { 220 .name = "CMT", 221 .start = 0x044a0060, 222 .end = 0x044a006b, 223 .flags = IORESOURCE_MEM, 224 }, 225 [1] = { 226 .start = 104, 227 .flags = IORESOURCE_IRQ, 228 }, 229 }; 230 231 static struct platform_device cmt_device = { 232 .name = "sh_cmt", 233 .id = 0, 234 .dev = { 235 .platform_data = &cmt_platform_data, 236 }, 237 .resource = cmt_resources, 238 .num_resources = ARRAY_SIZE(cmt_resources), 239 }; 240 241 static struct sh_timer_config tmu0_platform_data = { 242 .name = "TMU0", 243 .channel_offset = 0x04, 244 .timer_bit = 0, 245 .clk = "tmu0", 246 .clockevent_rating = 200, 247 }; 248 249 static struct resource tmu0_resources[] = { 250 [0] = { 251 .name = "TMU0", 252 .start = 0xffd80008, 253 .end = 0xffd80013, 254 .flags = IORESOURCE_MEM, 255 }, 256 [1] = { 257 .start = 16, 258 .flags = IORESOURCE_IRQ, 259 }, 260 }; 261 262 static struct platform_device tmu0_device = { 263 .name = "sh_tmu", 264 .id = 0, 265 .dev = { 266 .platform_data = &tmu0_platform_data, 267 }, 268 .resource = tmu0_resources, 269 .num_resources = ARRAY_SIZE(tmu0_resources), 270 }; 271 272 static struct sh_timer_config tmu1_platform_data = { 273 .name = "TMU1", 274 .channel_offset = 0x10, 275 .timer_bit = 1, 276 .clk = "tmu0", 277 .clocksource_rating = 200, 278 }; 279 280 static struct resource tmu1_resources[] = { 281 [0] = { 282 .name = "TMU1", 283 .start = 0xffd80014, 284 .end = 0xffd8001f, 285 .flags = IORESOURCE_MEM, 286 }, 287 [1] = { 288 .start = 17, 289 .flags = IORESOURCE_IRQ, 290 }, 291 }; 292 293 static struct platform_device tmu1_device = { 294 .name = "sh_tmu", 295 .id = 1, 296 .dev = { 297 .platform_data = &tmu1_platform_data, 298 }, 299 .resource = tmu1_resources, 300 .num_resources = ARRAY_SIZE(tmu1_resources), 301 }; 302 303 static struct sh_timer_config tmu2_platform_data = { 304 .name = "TMU2", 305 .channel_offset = 0x1c, 306 .timer_bit = 2, 307 .clk = "tmu0", 308 }; 309 310 static struct resource tmu2_resources[] = { 311 [0] = { 312 .name = "TMU2", 313 .start = 0xffd80020, 314 .end = 0xffd8002b, 315 .flags = IORESOURCE_MEM, 316 }, 317 [1] = { 318 .start = 18, 319 .flags = IORESOURCE_IRQ, 320 }, 321 }; 322 323 static struct platform_device tmu2_device = { 324 .name = "sh_tmu", 325 .id = 2, 326 .dev = { 327 .platform_data = &tmu2_platform_data, 328 }, 329 .resource = tmu2_resources, 330 .num_resources = ARRAY_SIZE(tmu2_resources), 331 }; 332 333 static struct platform_device *sh7343_devices[] __initdata = { 334 &scif0_device, 335 &scif1_device, 336 &scif2_device, 337 &scif3_device, 338 &cmt_device, 339 &tmu0_device, 340 &tmu1_device, 341 &tmu2_device, 342 &iic0_device, 343 &iic1_device, 344 &vpu_device, 345 &veu_device, 346 &jpu_device, 347 }; 348 349 static int __init sh7343_devices_setup(void) 350 { 351 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 352 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 353 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 354 355 return platform_add_devices(sh7343_devices, 356 ARRAY_SIZE(sh7343_devices)); 357 } 358 arch_initcall(sh7343_devices_setup); 359 360 static struct platform_device *sh7343_early_devices[] __initdata = { 361 &scif0_device, 362 &scif1_device, 363 &scif2_device, 364 &scif3_device, 365 &cmt_device, 366 &tmu0_device, 367 &tmu1_device, 368 &tmu2_device, 369 }; 370 371 void __init plat_early_device_setup(void) 372 { 373 early_platform_add_devices(sh7343_early_devices, 374 ARRAY_SIZE(sh7343_early_devices)); 375 } 376 377 enum { 378 UNUSED = 0, 379 380 /* interrupt sources */ 381 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 382 DMAC0, DMAC1, DMAC2, DMAC3, 383 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 384 MFI, VPU, TPU, Z3D4, USBI0, USBI1, 385 MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, 386 DMAC4, DMAC5, DMAC_DADERR, 387 KEYSC, 388 SCIF, SCIF1, SCIF2, SCIF3, 389 SIOF0, SIOF1, SIO, 390 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 391 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 392 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 393 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 394 IRDA, 395 SDHI0, SDHI1, SDHI2, SDHI3, 396 CMT, TSIF, SIU, 397 TMU0, TMU1, TMU2, 398 JPU, LCDC, 399 400 /* interrupt groups */ 401 402 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, 403 }; 404 405 static struct intc_vect vectors[] __initdata = { 406 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 407 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 408 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 409 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 410 INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), 411 INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), 412 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 413 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 414 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 415 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 416 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), 417 INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), 418 INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), 419 INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), 420 INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), 421 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 422 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 423 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), 424 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), 425 INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), 426 INTC_VECT(SIO, 0xd00), 427 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 428 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 429 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 430 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 431 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 432 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 433 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 434 INTC_VECT(SIU, 0xf80), 435 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 436 INTC_VECT(TMU2, 0x440), 437 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 438 }; 439 440 static struct intc_group groups[] __initdata = { 441 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 442 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 443 INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), 444 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 445 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 446 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 447 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 448 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 449 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 450 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), 451 INTC_GROUP(USB, USBI0, USBI1), 452 }; 453 454 static struct intc_mask_reg mask_registers[] __initdata = { 455 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 456 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 457 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 458 { 0, 0, 0, VPU, 0, 0, 0, MFI } }, 459 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 460 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 461 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 462 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 463 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 464 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, 465 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 466 { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, 467 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 468 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 469 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 470 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 471 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 472 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 473 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 474 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 475 { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, 476 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 477 { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, 478 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 479 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 480 }; 481 482 static struct intc_prio_reg prio_registers[] __initdata = { 483 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 484 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 485 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, 486 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 487 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, 488 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, 489 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, 490 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, 491 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, 492 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, 493 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 494 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 495 }; 496 497 static struct intc_sense_reg sense_registers[] __initdata = { 498 { 0xa414001c, 16, 2, /* ICR1 */ 499 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 500 }; 501 502 static struct intc_mask_reg ack_registers[] __initdata = { 503 { 0xa4140024, 0, 8, /* INTREQ00 */ 504 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 505 }; 506 507 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, 508 mask_registers, prio_registers, sense_registers, 509 ack_registers); 510 511 void __init plat_irq_setup(void) 512 { 513 register_intc_controller(&intc_desc); 514 } 515