1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c 3 * 4 * SH7785 support for the clock framework 5 * 6 * Copyright (C) 2007 - 2009 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/cpufreq.h> 17 #include <asm/clock.h> 18 #include <asm/freq.h> 19 #include <cpu/sh7785.h> 20 21 /* 22 * Default rate for the root input clock, reset this with clk_set_rate() 23 * from the platform code. 24 */ 25 static struct clk extal_clk = { 26 .name = "extal", 27 .id = -1, 28 .rate = 33333333, 29 }; 30 31 static unsigned long pll_recalc(struct clk *clk) 32 { 33 int multiplier; 34 35 multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; 36 37 return clk->parent->rate * multiplier; 38 } 39 40 static struct clk_ops pll_clk_ops = { 41 .recalc = pll_recalc, 42 }; 43 44 static struct clk pll_clk = { 45 .name = "pll_clk", 46 .id = -1, 47 .ops = &pll_clk_ops, 48 .parent = &extal_clk, 49 .flags = CLK_ENABLE_ON_INIT, 50 }; 51 52 static struct clk *clks[] = { 53 &extal_clk, 54 &pll_clk, 55 }; 56 57 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 58 24, 32, 36, 48 }; 59 60 static struct clk_div_mult_table div4_table = { 61 .divisors = div2, 62 .nr_divisors = ARRAY_SIZE(div2), 63 }; 64 65 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 66 DIV4_DU, DIV4_P, DIV4_NR }; 67 68 #define DIV4(_str, _bit, _mask, _flags) \ 69 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 70 71 struct clk div4_clks[DIV4_NR] = { 72 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), 73 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), 74 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), 75 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), 77 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), 78 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), 80 }; 81 82 #define MSTPCR0 0xffc80030 83 #define MSTPCR1 0xffc80034 84 85 static struct clk mstp_clks[] = { 86 /* MSTPCR0 */ 87 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 88 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 89 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 90 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 91 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 92 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 93 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 94 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 95 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 96 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 97 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 98 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 99 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 100 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 101 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 102 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 103 104 /* MSTPCR1 */ 105 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 106 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 107 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 108 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 109 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 110 }; 111 112 int __init arch_clk_init(void) 113 { 114 int i, ret = 0; 115 116 for (i = 0; i < ARRAY_SIZE(clks); i++) 117 ret |= clk_register(clks[i]); 118 119 if (!ret) 120 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 121 &div4_table); 122 if (!ret) 123 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 124 125 return ret; 126 } 127