1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7763.c 3 * 4 * SH7763 support for the clock framework 5 * 6 * Copyright (C) 2005 Paul Mundt 7 * Copyright (C) 2007 Yoshihiro Shimoda 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <asm/clock.h> 16 #include <asm/freq.h> 17 #include <asm/io.h> 18 19 static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; 20 static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; 21 static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 }; 22 static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; 23 24 static void master_clk_init(struct clk *clk) 25 { 26 clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; 27 } 28 29 static struct clk_ops sh7763_master_clk_ops = { 30 .init = master_clk_init, 31 }; 32 33 static void module_clk_recalc(struct clk *clk) 34 { 35 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 36 clk->rate = clk->parent->rate / p0fc_divisors[idx]; 37 } 38 39 static struct clk_ops sh7763_module_clk_ops = { 40 .recalc = module_clk_recalc, 41 }; 42 43 static void bus_clk_recalc(struct clk *clk) 44 { 45 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 46 clk->rate = clk->parent->rate / bfc_divisors[idx]; 47 } 48 49 static struct clk_ops sh7763_bus_clk_ops = { 50 .recalc = bus_clk_recalc, 51 }; 52 53 static void cpu_clk_recalc(struct clk *clk) 54 { 55 clk->rate = clk->parent->rate; 56 } 57 58 static struct clk_ops sh7763_cpu_clk_ops = { 59 .recalc = cpu_clk_recalc, 60 }; 61 62 static struct clk_ops *sh7763_clk_ops[] = { 63 &sh7763_master_clk_ops, 64 &sh7763_module_clk_ops, 65 &sh7763_bus_clk_ops, 66 &sh7763_cpu_clk_ops, 67 }; 68 69 void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 70 { 71 if (idx < ARRAY_SIZE(sh7763_clk_ops)) 72 *ops = sh7763_clk_ops[idx]; 73 } 74 75 static void shyway_clk_recalc(struct clk *clk) 76 { 77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 78 clk->rate = clk->parent->rate / cfc_divisors[idx]; 79 } 80 81 static struct clk_ops sh7763_shyway_clk_ops = { 82 .recalc = shyway_clk_recalc, 83 }; 84 85 static struct clk sh7763_shyway_clk = { 86 .name = "shyway_clk", 87 .flags = CLK_ALWAYS_ENABLED, 88 .ops = &sh7763_shyway_clk_ops, 89 }; 90 91 /* 92 * Additional SH7763-specific on-chip clocks that aren't already part of the 93 * clock framework 94 */ 95 static struct clk *sh7763_onchip_clocks[] = { 96 &sh7763_shyway_clk, 97 }; 98 99 static int __init sh7763_clk_init(void) 100 { 101 struct clk *clk = clk_get(NULL, "master_clk"); 102 int i; 103 104 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { 105 struct clk *clkp = sh7763_onchip_clocks[i]; 106 107 clkp->parent = clk; 108 clk_register(clkp); 109 clk_enable(clkp); 110 } 111 112 /* 113 * Now that we have the rest of the clocks registered, we need to 114 * force the parent clock to propagate so that these clocks will 115 * automatically figure out their rate. We cheat by handing the 116 * parent clock its current rate and forcing child propagation. 117 */ 118 clk_set_rate(clk, clk_get_rate(clk)); 119 120 clk_put(clk); 121 122 return 0; 123 } 124 125 arch_initcall(sh7763_clk_init); 126 127