1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * arch/sh/kernel/cpu/sh4/clock-sh7757.c
4  *
5  * SH7757 support for the clock framework
6  *
7  *  Copyright (C) 2009-2010  Renesas Solutions Corp.
8  */
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/io.h>
12 #include <linux/clkdev.h>
13 #include <asm/clock.h>
14 #include <asm/freq.h>
15 
16 /*
17  * Default rate for the root input clock, reset this with clk_set_rate()
18  * from the platform code.
19  */
20 static struct clk extal_clk = {
21 	.rate		= 48000000,
22 };
23 
24 static unsigned long pll_recalc(struct clk *clk)
25 {
26 	int multiplier;
27 
28 	multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
29 
30 	return clk->parent->rate * multiplier;
31 }
32 
33 static struct sh_clk_ops pll_clk_ops = {
34 	.recalc		= pll_recalc,
35 };
36 
37 static struct clk pll_clk = {
38 	.ops		= &pll_clk_ops,
39 	.parent		= &extal_clk,
40 	.flags		= CLK_ENABLE_ON_INIT,
41 };
42 
43 static struct clk *clks[] = {
44 	&extal_clk,
45 	&pll_clk,
46 };
47 
48 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
49 			       1, 1, 1, 16, 1, 24, 1, 1 };
50 
51 static struct clk_div_mult_table div4_div_mult_table = {
52 	.divisors = div2,
53 	.nr_divisors = ARRAY_SIZE(div2),
54 };
55 
56 static struct clk_div4_table div4_table = {
57 	.div_mult_table = &div4_div_mult_table,
58 };
59 
60 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
61 
62 #define DIV4(_bit, _mask, _flags) \
63   SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
64 
65 struct clk div4_clks[DIV4_NR] = {
66 	/*
67 	 * P clock is always enable, because some P clock modules is used
68 	 * by Host PC.
69 	 */
70 	[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
71 	[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
72 	[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
73 };
74 
75 #define MSTPCR0		0xffc80030
76 #define MSTPCR1		0xffc80034
77 #define MSTPCR2		0xffc10028
78 
79 enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112,
80        MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
81        MSTP_NR };
82 
83 static struct clk mstp_clks[MSTP_NR] = {
84 	/* MSTPCR0 */
85 	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
86 	[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
87 
88 	/* MSTPCR1 */
89 	[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
90 	[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
91 	[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
92 	[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
93 	[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
94 	[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
95 	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
96 	[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
97 
98 	/* MSTPCR2 */
99 	[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
100 };
101 
102 static struct clk_lookup lookups[] = {
103 	/* main clocks */
104 	CLKDEV_CON_ID("extal", &extal_clk),
105 	CLKDEV_CON_ID("pll_clk", &pll_clk),
106 
107 	/* DIV4 clocks */
108 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
109 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
110 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
111 
112 	/* MSTP32 clocks */
113 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
114 	CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
115 	CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
116 	CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
117 	CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
118 	CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
119 	CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
120 	CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
121 	CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
122 
123 	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
124 	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
125 	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP112]),
126 	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP111]),
127 	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
128 
129 	CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
130 	CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
131 	CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
132 	CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]),
133 };
134 
135 int __init arch_clk_init(void)
136 {
137 	int i, ret = 0;
138 
139 	for (i = 0; i < ARRAY_SIZE(clks); i++)
140 		ret |= clk_register(clks[i]);
141 
142 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
143 
144 	if (!ret)
145 		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
146 					   &div4_table);
147 	if (!ret)
148 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
149 
150 	return ret;
151 }
152 
153