1 /*
2  * arch/sh/kernel/cpu/sh4/clock-sh7757.c
3  *
4  * SH7757 support for the clock framework
5  *
6  *  Copyright (C) 2009  Renesas Solutions Corp.
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/io.h>
15 #include <asm/clock.h>
16 #include <asm/freq.h>
17 
18 static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
19 			      16, 1, 1, 32, 1, 1, 1, 1 };
20 static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
21 			      16, 1, 1, 32, 1, 1, 1, 1 };
22 static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
23 			      16, 1, 1, 32, 1, 1, 1, 1 };
24 static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
25 			       16, 1, 1, 32, 1, 1, 1, 1 };
26 
27 static void master_clk_init(struct clk *clk)
28 {
29 	clk->rate = CONFIG_SH_PCLK_FREQ * 16;
30 }
31 
32 static struct clk_ops sh7757_master_clk_ops = {
33 	.init		= master_clk_init,
34 };
35 
36 static void module_clk_recalc(struct clk *clk)
37 {
38 	int idx = ctrl_inl(FRQCR) & 0x0000000f;
39 	clk->rate = clk->parent->rate / p1fc_divisors[idx];
40 }
41 
42 static struct clk_ops sh7757_module_clk_ops = {
43 	.recalc		= module_clk_recalc,
44 };
45 
46 static void bus_clk_recalc(struct clk *clk)
47 {
48 	int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
49 	clk->rate = clk->parent->rate / bfc_divisors[idx];
50 }
51 
52 static struct clk_ops sh7757_bus_clk_ops = {
53 	.recalc		= bus_clk_recalc,
54 };
55 
56 static void cpu_clk_recalc(struct clk *clk)
57 {
58 	int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
59 	clk->rate = clk->parent->rate / ifc_divisors[idx];
60 }
61 
62 static struct clk_ops sh7757_cpu_clk_ops = {
63 	.recalc		= cpu_clk_recalc,
64 };
65 
66 static struct clk_ops *sh7757_clk_ops[] = {
67 	&sh7757_master_clk_ops,
68 	&sh7757_module_clk_ops,
69 	&sh7757_bus_clk_ops,
70 	&sh7757_cpu_clk_ops,
71 };
72 
73 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74 {
75 	if (idx < ARRAY_SIZE(sh7757_clk_ops))
76 		*ops = sh7757_clk_ops[idx];
77 }
78 
79 static void shyway_clk_recalc(struct clk *clk)
80 {
81 	int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
82 	clk->rate = clk->parent->rate / sfc_divisors[idx];
83 }
84 
85 static struct clk_ops sh7757_shyway_clk_ops = {
86 	.recalc		= shyway_clk_recalc,
87 };
88 
89 static struct clk sh7757_shyway_clk = {
90 	.name		= "shyway_clk",
91 	.flags		= CLK_ENABLE_ON_INIT,
92 	.ops		= &sh7757_shyway_clk_ops,
93 };
94 
95 /*
96  * Additional sh7757-specific on-chip clocks that aren't already part of the
97  * clock framework
98  */
99 static struct clk *sh7757_onchip_clocks[] = {
100 	&sh7757_shyway_clk,
101 };
102 
103 static int __init sh7757_clk_init(void)
104 {
105 	struct clk *clk = clk_get(NULL, "master_clk");
106 	int i;
107 
108 	for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
109 		struct clk *clkp = sh7757_onchip_clocks[i];
110 
111 		clkp->parent = clk;
112 		clk_register(clkp);
113 		clk_enable(clkp);
114 	}
115 
116 	/*
117 	 * Now that we have the rest of the clocks registered, we need to
118 	 * force the parent clock to propagate so that these clocks will
119 	 * automatically figure out their rate. We cheat by handing the
120 	 * parent clock its current rate and forcing child propagation.
121 	 */
122 	clk_set_rate(clk, clk_get_rate(clk));
123 
124 	clk_put(clk);
125 
126 	return 0;
127 }
128 
129 arch_initcall(sh7757_clk_init);
130 
131