1add5ca2cSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2c01f0f1aSYoshihiro Shimoda /*
3c01f0f1aSYoshihiro Shimoda * arch/sh/kernel/cpu/sh4/clock-sh7757.c
4c01f0f1aSYoshihiro Shimoda *
5c01f0f1aSYoshihiro Shimoda * SH7757 support for the clock framework
6c01f0f1aSYoshihiro Shimoda *
756c52986SYoshihiro Shimoda * Copyright (C) 2009-2010 Renesas Solutions Corp.
8c01f0f1aSYoshihiro Shimoda */
9c01f0f1aSYoshihiro Shimoda #include <linux/init.h>
10c01f0f1aSYoshihiro Shimoda #include <linux/kernel.h>
11c01f0f1aSYoshihiro Shimoda #include <linux/io.h>
126d803ba7SJean-Christop PLAGNIOL-VILLARD #include <linux/clkdev.h>
13c01f0f1aSYoshihiro Shimoda #include <asm/clock.h>
14c01f0f1aSYoshihiro Shimoda #include <asm/freq.h>
15c01f0f1aSYoshihiro Shimoda
16c01f0f1aSYoshihiro Shimoda /*
1756c52986SYoshihiro Shimoda * Default rate for the root input clock, reset this with clk_set_rate()
1856c52986SYoshihiro Shimoda * from the platform code.
19c01f0f1aSYoshihiro Shimoda */
2056c52986SYoshihiro Shimoda static struct clk extal_clk = {
2156c52986SYoshihiro Shimoda .rate = 48000000,
2256c52986SYoshihiro Shimoda };
2356c52986SYoshihiro Shimoda
pll_recalc(struct clk * clk)2456c52986SYoshihiro Shimoda static unsigned long pll_recalc(struct clk *clk)
2556c52986SYoshihiro Shimoda {
2656c52986SYoshihiro Shimoda int multiplier;
2756c52986SYoshihiro Shimoda
2856c52986SYoshihiro Shimoda multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
2956c52986SYoshihiro Shimoda
3056c52986SYoshihiro Shimoda return clk->parent->rate * multiplier;
3156c52986SYoshihiro Shimoda }
3256c52986SYoshihiro Shimoda
3333cb61a4SMagnus Damm static struct sh_clk_ops pll_clk_ops = {
3456c52986SYoshihiro Shimoda .recalc = pll_recalc,
3556c52986SYoshihiro Shimoda };
3656c52986SYoshihiro Shimoda
3756c52986SYoshihiro Shimoda static struct clk pll_clk = {
3856c52986SYoshihiro Shimoda .ops = &pll_clk_ops,
3956c52986SYoshihiro Shimoda .parent = &extal_clk,
4056c52986SYoshihiro Shimoda .flags = CLK_ENABLE_ON_INIT,
4156c52986SYoshihiro Shimoda };
4256c52986SYoshihiro Shimoda
4356c52986SYoshihiro Shimoda static struct clk *clks[] = {
4456c52986SYoshihiro Shimoda &extal_clk,
4556c52986SYoshihiro Shimoda &pll_clk,
4656c52986SYoshihiro Shimoda };
4756c52986SYoshihiro Shimoda
4856c52986SYoshihiro Shimoda static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
4956c52986SYoshihiro Shimoda 1, 1, 1, 16, 1, 24, 1, 1 };
5056c52986SYoshihiro Shimoda
5156c52986SYoshihiro Shimoda static struct clk_div_mult_table div4_div_mult_table = {
5256c52986SYoshihiro Shimoda .divisors = div2,
5356c52986SYoshihiro Shimoda .nr_divisors = ARRAY_SIZE(div2),
5456c52986SYoshihiro Shimoda };
5556c52986SYoshihiro Shimoda
5656c52986SYoshihiro Shimoda static struct clk_div4_table div4_table = {
5756c52986SYoshihiro Shimoda .div_mult_table = &div4_div_mult_table,
5856c52986SYoshihiro Shimoda };
5956c52986SYoshihiro Shimoda
6056c52986SYoshihiro Shimoda enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
6156c52986SYoshihiro Shimoda
6256c52986SYoshihiro Shimoda #define DIV4(_bit, _mask, _flags) \
6356c52986SYoshihiro Shimoda SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
6456c52986SYoshihiro Shimoda
6556c52986SYoshihiro Shimoda struct clk div4_clks[DIV4_NR] = {
6656c52986SYoshihiro Shimoda /*
6756c52986SYoshihiro Shimoda * P clock is always enable, because some P clock modules is used
6856c52986SYoshihiro Shimoda * by Host PC.
6956c52986SYoshihiro Shimoda */
7056c52986SYoshihiro Shimoda [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
7156c52986SYoshihiro Shimoda [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
7256c52986SYoshihiro Shimoda [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
7356c52986SYoshihiro Shimoda };
7456c52986SYoshihiro Shimoda
7556c52986SYoshihiro Shimoda #define MSTPCR0 0xffc80030
7656c52986SYoshihiro Shimoda #define MSTPCR1 0xffc80034
7753bc18efSYoshihiro Shimoda #define MSTPCR2 0xffc10028
7856c52986SYoshihiro Shimoda
79fb434065SShimoda, Yoshihiro enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112,
8053bc18efSYoshihiro Shimoda MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
8156c52986SYoshihiro Shimoda MSTP_NR };
8256c52986SYoshihiro Shimoda
8356c52986SYoshihiro Shimoda static struct clk mstp_clks[MSTP_NR] = {
8456c52986SYoshihiro Shimoda /* MSTPCR0 */
8556c52986SYoshihiro Shimoda [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
8656c52986SYoshihiro Shimoda [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
8756c52986SYoshihiro Shimoda
8856c52986SYoshihiro Shimoda /* MSTPCR1 */
89fb434065SShimoda, Yoshihiro [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
9056c52986SYoshihiro Shimoda [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
9156c52986SYoshihiro Shimoda [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
9256c52986SYoshihiro Shimoda [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
9356c52986SYoshihiro Shimoda [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
9456c52986SYoshihiro Shimoda [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
9556c52986SYoshihiro Shimoda [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
9656c52986SYoshihiro Shimoda [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
9753bc18efSYoshihiro Shimoda
9853bc18efSYoshihiro Shimoda /* MSTPCR2 */
9953bc18efSYoshihiro Shimoda [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
100c01f0f1aSYoshihiro Shimoda };
101c01f0f1aSYoshihiro Shimoda
102f0e7f902SMagnus Damm static struct clk_lookup lookups[] = {
103f0e7f902SMagnus Damm /* main clocks */
10456c52986SYoshihiro Shimoda CLKDEV_CON_ID("extal", &extal_clk),
10556c52986SYoshihiro Shimoda CLKDEV_CON_ID("pll_clk", &pll_clk),
10656c52986SYoshihiro Shimoda
10756c52986SYoshihiro Shimoda /* DIV4 clocks */
10856c52986SYoshihiro Shimoda CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
10956c52986SYoshihiro Shimoda CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
11056c52986SYoshihiro Shimoda CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
11156c52986SYoshihiro Shimoda
11256c52986SYoshihiro Shimoda /* MSTP32 clocks */
113a052d2c3SShimoda, Yoshihiro CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
1145261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
1155261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
1165261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
1175261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
1185261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
1195261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
1205261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
1215261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
1229b417571SKuninori Morimoto
1231399c195SLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
1241399c195SLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
125fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP112]),
126fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP111]),
127fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
1289b417571SKuninori Morimoto
1295261b0a2SYoshihiro Shimoda CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
1301760e371SShimoda, Yoshihiro CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
13153bc18efSYoshihiro Shimoda CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
132ba6e8b8fSGeert Uytterhoeven CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]),
133f0e7f902SMagnus Damm };
134f0e7f902SMagnus Damm
arch_clk_init(void)13556c52986SYoshihiro Shimoda int __init arch_clk_init(void)
136c01f0f1aSYoshihiro Shimoda {
13756c52986SYoshihiro Shimoda int i, ret = 0;
138c01f0f1aSYoshihiro Shimoda
13956c52986SYoshihiro Shimoda for (i = 0; i < ARRAY_SIZE(clks); i++)
14056c52986SYoshihiro Shimoda ret |= clk_register(clks[i]);
1418a7711fcSRussell King
1428a7711fcSRussell King clkdev_add_table(lookups, ARRAY_SIZE(lookups));
143c01f0f1aSYoshihiro Shimoda
14456c52986SYoshihiro Shimoda if (!ret)
14556c52986SYoshihiro Shimoda ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
14656c52986SYoshihiro Shimoda &div4_table);
14756c52986SYoshihiro Shimoda if (!ret)
148ad3337cbSNobuhiro Iwamatsu ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
14956c52986SYoshihiro Shimoda
15056c52986SYoshihiro Shimoda return ret;
151c01f0f1aSYoshihiro Shimoda }
152c01f0f1aSYoshihiro Shimoda
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