1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3 * 4 * SH7724 clock framework support 5 * 6 * Copyright (C) 2009 Magnus Damm 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <asm/clkdev.h> 26 #include <asm/clock.h> 27 #include <asm/hwblk.h> 28 #include <cpu/sh7724.h> 29 30 /* SH7724 registers */ 31 #define FRQCRA 0xa4150000 32 #define FRQCRB 0xa4150004 33 #define VCLKCR 0xa4150048 34 #define FCLKACR 0xa4150008 35 #define FCLKBCR 0xa415000c 36 #define IRDACLKCR 0xa4150018 37 #define PLLCR 0xa4150024 38 #define SPUCLKCR 0xa415003c 39 #define FLLFRQ 0xa4150050 40 #define LSTATS 0xa4150060 41 42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 43 static struct clk r_clk = { 44 .rate = 32768, 45 }; 46 47 /* 48 * Default rate for the root input clock, reset this with clk_set_rate() 49 * from the platform code. 50 */ 51 static struct clk extal_clk = { 52 .rate = 33333333, 53 }; 54 55 /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 56 static unsigned long fll_recalc(struct clk *clk) 57 { 58 unsigned long mult = 0; 59 unsigned long div = 1; 60 61 if (__raw_readl(PLLCR) & 0x1000) 62 mult = __raw_readl(FLLFRQ) & 0x3ff; 63 64 if (__raw_readl(FLLFRQ) & 0x4000) 65 div = 2; 66 67 return (clk->parent->rate * mult) / div; 68 } 69 70 static struct clk_ops fll_clk_ops = { 71 .recalc = fll_recalc, 72 }; 73 74 static struct clk fll_clk = { 75 .ops = &fll_clk_ops, 76 .parent = &r_clk, 77 .flags = CLK_ENABLE_ON_INIT, 78 }; 79 80 static unsigned long pll_recalc(struct clk *clk) 81 { 82 unsigned long mult = 1; 83 84 if (__raw_readl(PLLCR) & 0x4000) 85 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 86 87 return clk->parent->rate * mult; 88 } 89 90 static struct clk_ops pll_clk_ops = { 91 .recalc = pll_recalc, 92 }; 93 94 static struct clk pll_clk = { 95 .ops = &pll_clk_ops, 96 .flags = CLK_ENABLE_ON_INIT, 97 }; 98 99 /* A fixed divide-by-3 block use by the div6 clocks */ 100 static unsigned long div3_recalc(struct clk *clk) 101 { 102 return clk->parent->rate / 3; 103 } 104 105 static struct clk_ops div3_clk_ops = { 106 .recalc = div3_recalc, 107 }; 108 109 static struct clk div3_clk = { 110 .ops = &div3_clk_ops, 111 .parent = &pll_clk, 112 }; 113 114 static struct clk *main_clks[] = { 115 &r_clk, 116 &extal_clk, 117 &fll_clk, 118 &pll_clk, 119 &div3_clk, 120 }; 121 122 static void div4_kick(struct clk *clk) 123 { 124 unsigned long value; 125 126 /* set KICK bit in FRQCRA to update hardware setting */ 127 value = __raw_readl(FRQCRA); 128 value |= (1 << 31); 129 __raw_writel(value, FRQCRA); 130 } 131 132 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 133 134 static struct clk_div_mult_table div4_div_mult_table = { 135 .divisors = divisors, 136 .nr_divisors = ARRAY_SIZE(divisors), 137 }; 138 139 static struct clk_div4_table div4_table = { 140 .div_mult_table = &div4_div_mult_table, 141 .kick = div4_kick, 142 }; 143 144 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 145 146 #define DIV4(_reg, _bit, _mask, _flags) \ 147 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 148 149 struct clk div4_clks[DIV4_NR] = { 150 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 151 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), 154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 155 }; 156 157 enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 158 159 static struct clk div6_clks[DIV6_NR] = { 160 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 161 [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), 162 [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), 163 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 164 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 165 }; 166 167 static struct clk mstp_clks[HWBLK_NR] = { 168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 170 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 172 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 173 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 174 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 177 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 178 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 179 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 180 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 181 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 182 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 183 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 184 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 185 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 186 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 187 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 188 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 189 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 190 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 191 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 192 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 193 194 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 195 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 196 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 197 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 198 199 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 200 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 201 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 202 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 203 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 204 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 205 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 206 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 207 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 208 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 209 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 210 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 211 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 212 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 213 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 214 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 215 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 216 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 217 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 218 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 219 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 220 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 221 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 222 }; 223 224 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 225 226 static struct clk_lookup lookups[] = { 227 /* main clocks */ 228 CLKDEV_CON_ID("rclk", &r_clk), 229 CLKDEV_CON_ID("extal", &extal_clk), 230 CLKDEV_CON_ID("fll_clk", &fll_clk), 231 CLKDEV_CON_ID("pll_clk", &pll_clk), 232 CLKDEV_CON_ID("div3_clk", &div3_clk), 233 234 /* DIV4 clocks */ 235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 238 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 239 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), 240 241 /* DIV6 clocks */ 242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 244 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), 245 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 246 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 247 248 /* MSTP clocks */ 249 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 250 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 251 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 252 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), 253 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 254 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 255 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 256 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 257 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 258 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 259 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 260 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 261 { 262 /* TMU0 */ 263 .dev_id = "sh_tmu.0", 264 .con_id = "tmu_fck", 265 .clk = &mstp_clks[HWBLK_TMU0], 266 }, { 267 /* TMU1 */ 268 .dev_id = "sh_tmu.1", 269 .con_id = "tmu_fck", 270 .clk = &mstp_clks[HWBLK_TMU0], 271 }, { 272 /* TMU2 */ 273 .dev_id = "sh_tmu.2", 274 .con_id = "tmu_fck", 275 .clk = &mstp_clks[HWBLK_TMU0], 276 }, { 277 /* TMU3 */ 278 .dev_id = "sh_tmu.3", 279 .con_id = "tmu_fck", 280 .clk = &mstp_clks[HWBLK_TMU1], 281 }, 282 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 283 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 284 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 285 { 286 /* TMU4 */ 287 .dev_id = "sh_tmu.4", 288 .con_id = "tmu_fck", 289 .clk = &mstp_clks[HWBLK_TMU1], 290 }, { 291 /* TMU5 */ 292 .dev_id = "sh_tmu.5", 293 .con_id = "tmu_fck", 294 .clk = &mstp_clks[HWBLK_TMU1], 295 }, { 296 /* SCIF0 */ 297 .dev_id = "sh-sci.0", 298 .con_id = "sci_fck", 299 .clk = &mstp_clks[HWBLK_SCIF0], 300 }, { 301 /* SCIF1 */ 302 .dev_id = "sh-sci.1", 303 .con_id = "sci_fck", 304 .clk = &mstp_clks[HWBLK_SCIF1], 305 }, { 306 /* SCIF2 */ 307 .dev_id = "sh-sci.2", 308 .con_id = "sci_fck", 309 .clk = &mstp_clks[HWBLK_SCIF2], 310 }, { 311 /* SCIF3 */ 312 .dev_id = "sh-sci.3", 313 .con_id = "sci_fck", 314 .clk = &mstp_clks[HWBLK_SCIF3], 315 }, { 316 /* SCIF4 */ 317 .dev_id = "sh-sci.4", 318 .con_id = "sci_fck", 319 .clk = &mstp_clks[HWBLK_SCIF4], 320 }, { 321 /* SCIF5 */ 322 .dev_id = "sh-sci.5", 323 .con_id = "sci_fck", 324 .clk = &mstp_clks[HWBLK_SCIF5], 325 }, 326 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 327 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 328 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 329 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 330 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]), 331 CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]), 332 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 333 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 334 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 335 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 336 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 337 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 338 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 339 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 340 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 341 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 342 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 343 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 344 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 345 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 346 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 347 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 348 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 349 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 350 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 351 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 352 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 353 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 354 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 355 }; 356 357 int __init arch_clk_init(void) 358 { 359 int k, ret = 0; 360 361 /* autodetect extal or fll configuration */ 362 if (__raw_readl(PLLCR) & 0x1000) 363 pll_clk.parent = &fll_clk; 364 else 365 pll_clk.parent = &extal_clk; 366 367 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 368 ret = clk_register(main_clks[k]); 369 370 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 371 372 if (!ret) 373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 374 375 if (!ret) 376 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 377 378 if (!ret) 379 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 380 381 return ret; 382 } 383