1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3 * 4 * SH7724 clock framework support 5 * 6 * Copyright (C) 2009 Magnus Damm 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <linux/clkdev.h> 26 #include <asm/clock.h> 27 #include <asm/hwblk.h> 28 #include <cpu/sh7724.h> 29 30 /* SH7724 registers */ 31 #define FRQCRA 0xa4150000 32 #define FRQCRB 0xa4150004 33 #define VCLKCR 0xa4150048 34 #define FCLKACR 0xa4150008 35 #define FCLKBCR 0xa415000c 36 #define IRDACLKCR 0xa4150018 37 #define PLLCR 0xa4150024 38 #define SPUCLKCR 0xa415003c 39 #define FLLFRQ 0xa4150050 40 #define LSTATS 0xa4150060 41 42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 43 static struct clk r_clk = { 44 .rate = 32768, 45 }; 46 47 /* 48 * Default rate for the root input clock, reset this with clk_set_rate() 49 * from the platform code. 50 */ 51 static struct clk extal_clk = { 52 .rate = 33333333, 53 }; 54 55 /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 56 static unsigned long fll_recalc(struct clk *clk) 57 { 58 unsigned long mult = 0; 59 unsigned long div = 1; 60 61 if (__raw_readl(PLLCR) & 0x1000) 62 mult = __raw_readl(FLLFRQ) & 0x3ff; 63 64 if (__raw_readl(FLLFRQ) & 0x4000) 65 div = 2; 66 67 return (clk->parent->rate * mult) / div; 68 } 69 70 static struct clk_ops fll_clk_ops = { 71 .recalc = fll_recalc, 72 }; 73 74 static struct clk fll_clk = { 75 .ops = &fll_clk_ops, 76 .parent = &r_clk, 77 .flags = CLK_ENABLE_ON_INIT, 78 }; 79 80 static unsigned long pll_recalc(struct clk *clk) 81 { 82 unsigned long mult = 1; 83 84 if (__raw_readl(PLLCR) & 0x4000) 85 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 86 87 return clk->parent->rate * mult; 88 } 89 90 static struct clk_ops pll_clk_ops = { 91 .recalc = pll_recalc, 92 }; 93 94 static struct clk pll_clk = { 95 .ops = &pll_clk_ops, 96 .flags = CLK_ENABLE_ON_INIT, 97 }; 98 99 /* A fixed divide-by-3 block use by the div6 clocks */ 100 static unsigned long div3_recalc(struct clk *clk) 101 { 102 return clk->parent->rate / 3; 103 } 104 105 static struct clk_ops div3_clk_ops = { 106 .recalc = div3_recalc, 107 }; 108 109 static struct clk div3_clk = { 110 .ops = &div3_clk_ops, 111 .parent = &pll_clk, 112 }; 113 114 /* External input clock (pin name: FSIMCKA/FSIMCKB ) */ 115 struct clk sh7724_fsimcka_clk = { 116 }; 117 118 struct clk sh7724_fsimckb_clk = { 119 }; 120 121 static struct clk *main_clks[] = { 122 &r_clk, 123 &extal_clk, 124 &fll_clk, 125 &pll_clk, 126 &div3_clk, 127 &sh7724_fsimcka_clk, 128 &sh7724_fsimckb_clk, 129 }; 130 131 static void div4_kick(struct clk *clk) 132 { 133 unsigned long value; 134 135 /* set KICK bit in FRQCRA to update hardware setting */ 136 value = __raw_readl(FRQCRA); 137 value |= (1 << 31); 138 __raw_writel(value, FRQCRA); 139 } 140 141 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 142 143 static struct clk_div_mult_table div4_div_mult_table = { 144 .divisors = divisors, 145 .nr_divisors = ARRAY_SIZE(divisors), 146 }; 147 148 static struct clk_div4_table div4_table = { 149 .div_mult_table = &div4_div_mult_table, 150 .kick = div4_kick, 151 }; 152 153 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 154 155 #define DIV4(_reg, _bit, _mask, _flags) \ 156 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 157 158 struct clk div4_clks[DIV4_NR] = { 159 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 160 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 161 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 162 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), 163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 164 }; 165 166 enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR }; 167 168 static struct clk div6_clks[DIV6_NR] = { 169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 172 }; 173 174 enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR }; 175 176 /* Indices are important - they are the actual src selecting values */ 177 static struct clk *fclkacr_parent[] = { 178 [0] = &div3_clk, 179 [1] = NULL, 180 [2] = &sh7724_fsimcka_clk, 181 [3] = NULL, 182 }; 183 184 static struct clk *fclkbcr_parent[] = { 185 [0] = &div3_clk, 186 [1] = NULL, 187 [2] = &sh7724_fsimckb_clk, 188 [3] = NULL, 189 }; 190 191 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0, 193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), 194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0, 195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), 196 }; 197 198 static struct clk mstp_clks[HWBLK_NR] = { 199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 224 225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 229 230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 253 }; 254 255 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 256 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 257 258 static struct clk_lookup lookups[] = { 259 /* main clocks */ 260 CLKDEV_CON_ID("rclk", &r_clk), 261 CLKDEV_CON_ID("extal", &extal_clk), 262 CLKDEV_CON_ID("fll_clk", &fll_clk), 263 CLKDEV_CON_ID("pll_clk", &pll_clk), 264 CLKDEV_CON_ID("div3_clk", &div3_clk), 265 266 /* DIV4 clocks */ 267 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 268 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 269 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 270 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 271 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), 272 273 /* DIV6 clocks */ 274 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 275 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]), 276 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]), 277 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 278 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 279 280 /* MSTP clocks */ 281 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 282 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 283 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 284 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), 285 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 286 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 287 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 288 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 289 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 290 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 291 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 292 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 293 { 294 /* TMU0 */ 295 .dev_id = "sh_tmu.0", 296 .con_id = "tmu_fck", 297 .clk = &mstp_clks[HWBLK_TMU0], 298 }, { 299 /* TMU1 */ 300 .dev_id = "sh_tmu.1", 301 .con_id = "tmu_fck", 302 .clk = &mstp_clks[HWBLK_TMU0], 303 }, { 304 /* TMU2 */ 305 .dev_id = "sh_tmu.2", 306 .con_id = "tmu_fck", 307 .clk = &mstp_clks[HWBLK_TMU0], 308 }, { 309 /* TMU3 */ 310 .dev_id = "sh_tmu.3", 311 .con_id = "tmu_fck", 312 .clk = &mstp_clks[HWBLK_TMU1], 313 }, 314 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 315 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 316 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 317 { 318 /* TMU4 */ 319 .dev_id = "sh_tmu.4", 320 .con_id = "tmu_fck", 321 .clk = &mstp_clks[HWBLK_TMU1], 322 }, { 323 /* TMU5 */ 324 .dev_id = "sh_tmu.5", 325 .con_id = "tmu_fck", 326 .clk = &mstp_clks[HWBLK_TMU1], 327 }, { 328 /* SCIF0 */ 329 .dev_id = "sh-sci.0", 330 .con_id = "sci_fck", 331 .clk = &mstp_clks[HWBLK_SCIF0], 332 }, { 333 /* SCIF1 */ 334 .dev_id = "sh-sci.1", 335 .con_id = "sci_fck", 336 .clk = &mstp_clks[HWBLK_SCIF1], 337 }, { 338 /* SCIF2 */ 339 .dev_id = "sh-sci.2", 340 .con_id = "sci_fck", 341 .clk = &mstp_clks[HWBLK_SCIF2], 342 }, { 343 /* SCIF3 */ 344 .dev_id = "sh-sci.3", 345 .con_id = "sci_fck", 346 .clk = &mstp_clks[HWBLK_SCIF3], 347 }, { 348 /* SCIF4 */ 349 .dev_id = "sh-sci.4", 350 .con_id = "sci_fck", 351 .clk = &mstp_clks[HWBLK_SCIF4], 352 }, { 353 /* SCIF5 */ 354 .dev_id = "sh-sci.5", 355 .con_id = "sci_fck", 356 .clk = &mstp_clks[HWBLK_SCIF5], 357 }, 358 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 359 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 360 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 361 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 362 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), 363 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), 364 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 365 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 366 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 367 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 368 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 369 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 370 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 371 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 372 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 373 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 374 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 375 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 376 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 377 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 378 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 379 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 380 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 381 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 382 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 383 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 384 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 385 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 386 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 387 }; 388 389 int __init arch_clk_init(void) 390 { 391 int k, ret = 0; 392 393 /* autodetect extal or fll configuration */ 394 if (__raw_readl(PLLCR) & 0x1000) 395 pll_clk.parent = &fll_clk; 396 else 397 pll_clk.parent = &extal_clk; 398 399 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 400 ret = clk_register(main_clks[k]); 401 402 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 403 404 if (!ret) 405 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 406 407 if (!ret) 408 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 409 410 if (!ret) 411 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); 412 413 if (!ret) 414 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 415 416 return ret; 417 } 418