1b621370aSMagnus Damm /* 2b621370aSMagnus Damm * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3b621370aSMagnus Damm * 4b621370aSMagnus Damm * SH7724 clock framework support 5b621370aSMagnus Damm * 6b621370aSMagnus Damm * Copyright (C) 2009 Magnus Damm 7b621370aSMagnus Damm * 8b621370aSMagnus Damm * This program is free software; you can redistribute it and/or modify 9b621370aSMagnus Damm * it under the terms of the GNU General Public License as published by 10b621370aSMagnus Damm * the Free Software Foundation; either version 2 of the License 11b621370aSMagnus Damm * 12b621370aSMagnus Damm * This program is distributed in the hope that it will be useful, 13b621370aSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b621370aSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b621370aSMagnus Damm * GNU General Public License for more details. 16b621370aSMagnus Damm * 17b621370aSMagnus Damm * You should have received a copy of the GNU General Public License 18b621370aSMagnus Damm * along with this program; if not, write to the Free Software 19b621370aSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b621370aSMagnus Damm */ 21b621370aSMagnus Damm #include <linux/init.h> 22b621370aSMagnus Damm #include <linux/kernel.h> 23b621370aSMagnus Damm #include <linux/io.h> 24f4cff0d0SPaul Mundt #include <linux/clk.h> 25f4cff0d0SPaul Mundt #include <asm/clkdev.h> 26b621370aSMagnus Damm #include <asm/clock.h> 276ba4a8f0SMagnus Damm #include <asm/hwblk.h> 286ba4a8f0SMagnus Damm #include <cpu/sh7724.h> 29b621370aSMagnus Damm 30b621370aSMagnus Damm /* SH7724 registers */ 31b621370aSMagnus Damm #define FRQCRA 0xa4150000 32b621370aSMagnus Damm #define FRQCRB 0xa4150004 33b621370aSMagnus Damm #define VCLKCR 0xa4150048 34b621370aSMagnus Damm #define FCLKACR 0xa4150008 35b621370aSMagnus Damm #define FCLKBCR 0xa415000c 36b621370aSMagnus Damm #define IRDACLKCR 0xa4150018 37b621370aSMagnus Damm #define PLLCR 0xa4150024 38b621370aSMagnus Damm #define SPUCLKCR 0xa415003c 39b621370aSMagnus Damm #define FLLFRQ 0xa4150050 40b621370aSMagnus Damm #define LSTATS 0xa4150060 41b621370aSMagnus Damm 42b621370aSMagnus Damm /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 43b621370aSMagnus Damm static struct clk r_clk = { 44b621370aSMagnus Damm .name = "rclk", 45b621370aSMagnus Damm .id = -1, 46b621370aSMagnus Damm .rate = 32768, 47b621370aSMagnus Damm }; 48b621370aSMagnus Damm 49b621370aSMagnus Damm /* 50b621370aSMagnus Damm * Default rate for the root input clock, reset this with clk_set_rate() 51b621370aSMagnus Damm * from the platform code. 52b621370aSMagnus Damm */ 53b621370aSMagnus Damm struct clk extal_clk = { 54b621370aSMagnus Damm .name = "extal", 55b621370aSMagnus Damm .id = -1, 56b621370aSMagnus Damm .rate = 33333333, 57b621370aSMagnus Damm }; 58b621370aSMagnus Damm 59b621370aSMagnus Damm /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 60b621370aSMagnus Damm static unsigned long fll_recalc(struct clk *clk) 61b621370aSMagnus Damm { 62b621370aSMagnus Damm unsigned long mult = 0; 63b621370aSMagnus Damm unsigned long div = 1; 64b621370aSMagnus Damm 65b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 66b621370aSMagnus Damm mult = __raw_readl(FLLFRQ) & 0x3ff; 67b621370aSMagnus Damm 68b621370aSMagnus Damm if (__raw_readl(FLLFRQ) & 0x4000) 69b621370aSMagnus Damm div = 2; 70b621370aSMagnus Damm 71b621370aSMagnus Damm return (clk->parent->rate * mult) / div; 72b621370aSMagnus Damm } 73b621370aSMagnus Damm 74b621370aSMagnus Damm static struct clk_ops fll_clk_ops = { 75b621370aSMagnus Damm .recalc = fll_recalc, 76b621370aSMagnus Damm }; 77b621370aSMagnus Damm 78b621370aSMagnus Damm static struct clk fll_clk = { 79b621370aSMagnus Damm .name = "fll_clk", 80b621370aSMagnus Damm .id = -1, 81b621370aSMagnus Damm .ops = &fll_clk_ops, 82b621370aSMagnus Damm .parent = &r_clk, 83b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 84b621370aSMagnus Damm }; 85b621370aSMagnus Damm 86b621370aSMagnus Damm static unsigned long pll_recalc(struct clk *clk) 87b621370aSMagnus Damm { 88b621370aSMagnus Damm unsigned long mult = 1; 89b621370aSMagnus Damm 90b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x4000) 91b621370aSMagnus Damm mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 92b621370aSMagnus Damm 93b621370aSMagnus Damm return clk->parent->rate * mult; 94b621370aSMagnus Damm } 95b621370aSMagnus Damm 96b621370aSMagnus Damm static struct clk_ops pll_clk_ops = { 97b621370aSMagnus Damm .recalc = pll_recalc, 98b621370aSMagnus Damm }; 99b621370aSMagnus Damm 100b621370aSMagnus Damm static struct clk pll_clk = { 101b621370aSMagnus Damm .name = "pll_clk", 102b621370aSMagnus Damm .id = -1, 103b621370aSMagnus Damm .ops = &pll_clk_ops, 104b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 105b621370aSMagnus Damm }; 106b621370aSMagnus Damm 107b621370aSMagnus Damm /* A fixed divide-by-3 block use by the div6 clocks */ 108b621370aSMagnus Damm static unsigned long div3_recalc(struct clk *clk) 109b621370aSMagnus Damm { 110b621370aSMagnus Damm return clk->parent->rate / 3; 111b621370aSMagnus Damm } 112b621370aSMagnus Damm 113b621370aSMagnus Damm static struct clk_ops div3_clk_ops = { 114b621370aSMagnus Damm .recalc = div3_recalc, 115b621370aSMagnus Damm }; 116b621370aSMagnus Damm 117b621370aSMagnus Damm static struct clk div3_clk = { 118b621370aSMagnus Damm .name = "div3_clk", 119b621370aSMagnus Damm .id = -1, 120b621370aSMagnus Damm .ops = &div3_clk_ops, 121b621370aSMagnus Damm .parent = &pll_clk, 122b621370aSMagnus Damm }; 123b621370aSMagnus Damm 124b621370aSMagnus Damm struct clk *main_clks[] = { 125b621370aSMagnus Damm &r_clk, 126b621370aSMagnus Damm &extal_clk, 127b621370aSMagnus Damm &fll_clk, 128b621370aSMagnus Damm &pll_clk, 129b621370aSMagnus Damm &div3_clk, 130b621370aSMagnus Damm }; 131b621370aSMagnus Damm 1327be85c6eSMagnus Damm static void div4_kick(struct clk *clk) 1337be85c6eSMagnus Damm { 1347be85c6eSMagnus Damm unsigned long value; 1357be85c6eSMagnus Damm 1367be85c6eSMagnus Damm /* set KICK bit in FRQCRA to update hardware setting */ 1377be85c6eSMagnus Damm value = __raw_readl(FRQCRA); 1387be85c6eSMagnus Damm value |= (1 << 31); 1397be85c6eSMagnus Damm __raw_writel(value, FRQCRA); 1407be85c6eSMagnus Damm } 1417be85c6eSMagnus Damm 142b2ea8b42SKuninori Morimoto static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 143b621370aSMagnus Damm 1440a5f337eSMagnus Damm static struct clk_div_mult_table div4_div_mult_table = { 145b621370aSMagnus Damm .divisors = divisors, 146b621370aSMagnus Damm .nr_divisors = ARRAY_SIZE(divisors), 147b621370aSMagnus Damm }; 148b621370aSMagnus Damm 1490a5f337eSMagnus Damm static struct clk_div4_table div4_table = { 1500a5f337eSMagnus Damm .div_mult_table = &div4_div_mult_table, 1517be85c6eSMagnus Damm .kick = div4_kick, 1520a5f337eSMagnus Damm }; 1530a5f337eSMagnus Damm 154b621370aSMagnus Damm enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 155b621370aSMagnus Damm 156b621370aSMagnus Damm #define DIV4(_str, _reg, _bit, _mask, _flags) \ 157b621370aSMagnus Damm SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 158b621370aSMagnus Damm 159b621370aSMagnus Damm struct clk div4_clks[DIV4_NR] = { 160b621370aSMagnus Damm [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 161b621370aSMagnus Damm [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 162b621370aSMagnus Damm [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 163b621370aSMagnus Damm [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 1646f26d19fSMagnus Damm [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 165b621370aSMagnus Damm }; 166b621370aSMagnus Damm 167b621370aSMagnus Damm struct clk div6_clks[] = { 168b621370aSMagnus Damm SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), 169b621370aSMagnus Damm SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 170b621370aSMagnus Damm SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 171b621370aSMagnus Damm SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 172d1b261efSPaul Mundt SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 173b621370aSMagnus Damm }; 174b621370aSMagnus Damm 1756ba4a8f0SMagnus Damm #define R_CLK (&r_clk) 1766ba4a8f0SMagnus Damm #define P_CLK (&div4_clks[DIV4_P]) 1776ba4a8f0SMagnus Damm #define B_CLK (&div4_clks[DIV4_B]) 1786ba4a8f0SMagnus Damm #define I_CLK (&div4_clks[DIV4_I]) 1796ba4a8f0SMagnus Damm #define SH_CLK (&div4_clks[DIV4_SH]) 180b621370aSMagnus Damm 181f3d51e13SMagnus Damm static struct clk mstp_clks[HWBLK_NR] = { 1826ba4a8f0SMagnus Damm SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 1836ba4a8f0SMagnus Damm SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 1846ba4a8f0SMagnus Damm SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 1856ba4a8f0SMagnus Damm SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT), 1866ba4a8f0SMagnus Damm SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 1876ba4a8f0SMagnus Damm SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 1886ba4a8f0SMagnus Damm SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 1896ba4a8f0SMagnus Damm SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 1906ba4a8f0SMagnus Damm SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 1916ba4a8f0SMagnus Damm SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 1926ba4a8f0SMagnus Damm SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 1936ba4a8f0SMagnus Damm SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 194f4cff0d0SPaul Mundt SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0), 195f4cff0d0SPaul Mundt SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0), 1966ba4a8f0SMagnus Damm SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 1976ba4a8f0SMagnus Damm SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 198f4cff0d0SPaul Mundt SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0), 199e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF0, 0), 200e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF1, 0), 201e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF2, 0), 202e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF3, 0), 203e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF4, 0), 204e4e06697SMagnus Damm SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF5, 0), 2056ba4a8f0SMagnus Damm SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 2066ba4a8f0SMagnus Damm SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 207b621370aSMagnus Damm 2086ba4a8f0SMagnus Damm SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 2096ba4a8f0SMagnus Damm SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 2106ba4a8f0SMagnus Damm SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0), 2116ba4a8f0SMagnus Damm SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0), 212b621370aSMagnus Damm 2136ba4a8f0SMagnus Damm SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0), 2146ba4a8f0SMagnus Damm SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0), 2156ba4a8f0SMagnus Damm SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0), 2166ba4a8f0SMagnus Damm SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 2176ba4a8f0SMagnus Damm SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 2186ba4a8f0SMagnus Damm SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 2196ba4a8f0SMagnus Damm SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0), 2206ba4a8f0SMagnus Damm SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0), 2216ba4a8f0SMagnus Damm SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 2226ba4a8f0SMagnus Damm SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 2236ba4a8f0SMagnus Damm SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 224cc58f597SMagnus Damm SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0), 2256ba4a8f0SMagnus Damm SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0), 2266ba4a8f0SMagnus Damm SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0), 2276ba4a8f0SMagnus Damm SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0), 2286ba4a8f0SMagnus Damm SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0), 229cc58f597SMagnus Damm SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 2306ba4a8f0SMagnus Damm SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 2316ba4a8f0SMagnus Damm SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0), 2326ba4a8f0SMagnus Damm SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0), 233cc58f597SMagnus Damm SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0), 234cc58f597SMagnus Damm SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 2356ba4a8f0SMagnus Damm SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 236b621370aSMagnus Damm }; 237b621370aSMagnus Damm 238f4cff0d0SPaul Mundt static struct clk_lookup lookups[] = { 239f4cff0d0SPaul Mundt { 240f4cff0d0SPaul Mundt /* TMU0 */ 241f4cff0d0SPaul Mundt .dev_id = "sh_tmu.0", 242f4cff0d0SPaul Mundt .con_id = "tmu_fck", 243f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 244f4cff0d0SPaul Mundt }, { 245f4cff0d0SPaul Mundt /* TMU1 */ 246f4cff0d0SPaul Mundt .dev_id = "sh_tmu.1", 247f4cff0d0SPaul Mundt .con_id = "tmu_fck", 248f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 249f4cff0d0SPaul Mundt }, { 250f4cff0d0SPaul Mundt /* TMU2 */ 251f4cff0d0SPaul Mundt .dev_id = "sh_tmu.2", 252f4cff0d0SPaul Mundt .con_id = "tmu_fck", 253f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 254f4cff0d0SPaul Mundt }, { 255f4cff0d0SPaul Mundt /* TMU3 */ 256f4cff0d0SPaul Mundt .dev_id = "sh_tmu.3", 257f4cff0d0SPaul Mundt .con_id = "tmu_fck", 258f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 259f4cff0d0SPaul Mundt }, { 260f4cff0d0SPaul Mundt /* TMU4 */ 261f4cff0d0SPaul Mundt .dev_id = "sh_tmu.4", 262f4cff0d0SPaul Mundt .con_id = "tmu_fck", 263f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 264f4cff0d0SPaul Mundt }, { 265f4cff0d0SPaul Mundt /* TMU5 */ 266f4cff0d0SPaul Mundt .dev_id = "sh_tmu.5", 267f4cff0d0SPaul Mundt .con_id = "tmu_fck", 268f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 269e4e06697SMagnus Damm }, { 270e4e06697SMagnus Damm /* SCIF0 */ 271e4e06697SMagnus Damm .dev_id = "sh-sci.0", 272e4e06697SMagnus Damm .con_id = "sci_fck", 273e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF0], 274e4e06697SMagnus Damm }, { 275e4e06697SMagnus Damm /* SCIF1 */ 276e4e06697SMagnus Damm .dev_id = "sh-sci.1", 277e4e06697SMagnus Damm .con_id = "sci_fck", 278e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF1], 279e4e06697SMagnus Damm }, { 280e4e06697SMagnus Damm /* SCIF2 */ 281e4e06697SMagnus Damm .dev_id = "sh-sci.2", 282e4e06697SMagnus Damm .con_id = "sci_fck", 283e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF2], 284e4e06697SMagnus Damm }, { 285e4e06697SMagnus Damm /* SCIF3 */ 286e4e06697SMagnus Damm .dev_id = "sh-sci.3", 287e4e06697SMagnus Damm .con_id = "sci_fck", 288e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF3], 289e4e06697SMagnus Damm }, { 290e4e06697SMagnus Damm /* SCIF4 */ 291e4e06697SMagnus Damm .dev_id = "sh-sci.4", 292e4e06697SMagnus Damm .con_id = "sci_fck", 293e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF4], 294e4e06697SMagnus Damm }, { 295e4e06697SMagnus Damm /* SCIF5 */ 296e4e06697SMagnus Damm .dev_id = "sh-sci.5", 297e4e06697SMagnus Damm .con_id = "sci_fck", 298e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF5], 299f4cff0d0SPaul Mundt }, 300f4cff0d0SPaul Mundt }; 301f4cff0d0SPaul Mundt 302b621370aSMagnus Damm int __init arch_clk_init(void) 303b621370aSMagnus Damm { 304b621370aSMagnus Damm int k, ret = 0; 305b621370aSMagnus Damm 306b621370aSMagnus Damm /* autodetect extal or fll configuration */ 307b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 308b621370aSMagnus Damm pll_clk.parent = &fll_clk; 309b621370aSMagnus Damm else 310b621370aSMagnus Damm pll_clk.parent = &extal_clk; 311b621370aSMagnus Damm 312b621370aSMagnus Damm for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 313b621370aSMagnus Damm ret = clk_register(main_clks[k]); 314b621370aSMagnus Damm 315f4cff0d0SPaul Mundt clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 316f4cff0d0SPaul Mundt 317b621370aSMagnus Damm if (!ret) 318b621370aSMagnus Damm ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 319b621370aSMagnus Damm 320b621370aSMagnus Damm if (!ret) 321b621370aSMagnus Damm ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 322b621370aSMagnus Damm 323b621370aSMagnus Damm if (!ret) 324f3d51e13SMagnus Damm ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 325b621370aSMagnus Damm 326b621370aSMagnus Damm return ret; 327b621370aSMagnus Damm } 328