1b621370aSMagnus Damm /* 2b621370aSMagnus Damm * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3b621370aSMagnus Damm * 4b621370aSMagnus Damm * SH7724 clock framework support 5b621370aSMagnus Damm * 6b621370aSMagnus Damm * Copyright (C) 2009 Magnus Damm 7b621370aSMagnus Damm * 8b621370aSMagnus Damm * This program is free software; you can redistribute it and/or modify 9b621370aSMagnus Damm * it under the terms of the GNU General Public License as published by 10b621370aSMagnus Damm * the Free Software Foundation; either version 2 of the License 11b621370aSMagnus Damm * 12b621370aSMagnus Damm * This program is distributed in the hope that it will be useful, 13b621370aSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b621370aSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b621370aSMagnus Damm * GNU General Public License for more details. 16b621370aSMagnus Damm * 17b621370aSMagnus Damm * You should have received a copy of the GNU General Public License 18b621370aSMagnus Damm * along with this program; if not, write to the Free Software 19b621370aSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b621370aSMagnus Damm */ 21b621370aSMagnus Damm #include <linux/init.h> 22b621370aSMagnus Damm #include <linux/kernel.h> 23b621370aSMagnus Damm #include <linux/io.h> 24b621370aSMagnus Damm #include <asm/clock.h> 256ba4a8f0SMagnus Damm #include <asm/hwblk.h> 266ba4a8f0SMagnus Damm #include <cpu/sh7724.h> 27b621370aSMagnus Damm 28b621370aSMagnus Damm /* SH7724 registers */ 29b621370aSMagnus Damm #define FRQCRA 0xa4150000 30b621370aSMagnus Damm #define FRQCRB 0xa4150004 31b621370aSMagnus Damm #define VCLKCR 0xa4150048 32b621370aSMagnus Damm #define FCLKACR 0xa4150008 33b621370aSMagnus Damm #define FCLKBCR 0xa415000c 34b621370aSMagnus Damm #define IRDACLKCR 0xa4150018 35b621370aSMagnus Damm #define PLLCR 0xa4150024 36b621370aSMagnus Damm #define SPUCLKCR 0xa415003c 37b621370aSMagnus Damm #define FLLFRQ 0xa4150050 38b621370aSMagnus Damm #define LSTATS 0xa4150060 39b621370aSMagnus Damm 40b621370aSMagnus Damm /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 41b621370aSMagnus Damm static struct clk r_clk = { 42b621370aSMagnus Damm .name = "rclk", 43b621370aSMagnus Damm .id = -1, 44b621370aSMagnus Damm .rate = 32768, 45b621370aSMagnus Damm }; 46b621370aSMagnus Damm 47b621370aSMagnus Damm /* 48b621370aSMagnus Damm * Default rate for the root input clock, reset this with clk_set_rate() 49b621370aSMagnus Damm * from the platform code. 50b621370aSMagnus Damm */ 51b621370aSMagnus Damm struct clk extal_clk = { 52b621370aSMagnus Damm .name = "extal", 53b621370aSMagnus Damm .id = -1, 54b621370aSMagnus Damm .rate = 33333333, 55b621370aSMagnus Damm }; 56b621370aSMagnus Damm 57b621370aSMagnus Damm /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 58b621370aSMagnus Damm static unsigned long fll_recalc(struct clk *clk) 59b621370aSMagnus Damm { 60b621370aSMagnus Damm unsigned long mult = 0; 61b621370aSMagnus Damm unsigned long div = 1; 62b621370aSMagnus Damm 63b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 64b621370aSMagnus Damm mult = __raw_readl(FLLFRQ) & 0x3ff; 65b621370aSMagnus Damm 66b621370aSMagnus Damm if (__raw_readl(FLLFRQ) & 0x4000) 67b621370aSMagnus Damm div = 2; 68b621370aSMagnus Damm 69b621370aSMagnus Damm return (clk->parent->rate * mult) / div; 70b621370aSMagnus Damm } 71b621370aSMagnus Damm 72b621370aSMagnus Damm static struct clk_ops fll_clk_ops = { 73b621370aSMagnus Damm .recalc = fll_recalc, 74b621370aSMagnus Damm }; 75b621370aSMagnus Damm 76b621370aSMagnus Damm static struct clk fll_clk = { 77b621370aSMagnus Damm .name = "fll_clk", 78b621370aSMagnus Damm .id = -1, 79b621370aSMagnus Damm .ops = &fll_clk_ops, 80b621370aSMagnus Damm .parent = &r_clk, 81b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 82b621370aSMagnus Damm }; 83b621370aSMagnus Damm 84b621370aSMagnus Damm static unsigned long pll_recalc(struct clk *clk) 85b621370aSMagnus Damm { 86b621370aSMagnus Damm unsigned long mult = 1; 87b621370aSMagnus Damm 88b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x4000) 89b621370aSMagnus Damm mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 90b621370aSMagnus Damm 91b621370aSMagnus Damm return clk->parent->rate * mult; 92b621370aSMagnus Damm } 93b621370aSMagnus Damm 94b621370aSMagnus Damm static struct clk_ops pll_clk_ops = { 95b621370aSMagnus Damm .recalc = pll_recalc, 96b621370aSMagnus Damm }; 97b621370aSMagnus Damm 98b621370aSMagnus Damm static struct clk pll_clk = { 99b621370aSMagnus Damm .name = "pll_clk", 100b621370aSMagnus Damm .id = -1, 101b621370aSMagnus Damm .ops = &pll_clk_ops, 102b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 103b621370aSMagnus Damm }; 104b621370aSMagnus Damm 105b621370aSMagnus Damm /* A fixed divide-by-3 block use by the div6 clocks */ 106b621370aSMagnus Damm static unsigned long div3_recalc(struct clk *clk) 107b621370aSMagnus Damm { 108b621370aSMagnus Damm return clk->parent->rate / 3; 109b621370aSMagnus Damm } 110b621370aSMagnus Damm 111b621370aSMagnus Damm static struct clk_ops div3_clk_ops = { 112b621370aSMagnus Damm .recalc = div3_recalc, 113b621370aSMagnus Damm }; 114b621370aSMagnus Damm 115b621370aSMagnus Damm static struct clk div3_clk = { 116b621370aSMagnus Damm .name = "div3_clk", 117b621370aSMagnus Damm .id = -1, 118b621370aSMagnus Damm .ops = &div3_clk_ops, 119b621370aSMagnus Damm .parent = &pll_clk, 120b621370aSMagnus Damm }; 121b621370aSMagnus Damm 122b621370aSMagnus Damm struct clk *main_clks[] = { 123b621370aSMagnus Damm &r_clk, 124b621370aSMagnus Damm &extal_clk, 125b621370aSMagnus Damm &fll_clk, 126b621370aSMagnus Damm &pll_clk, 127b621370aSMagnus Damm &div3_clk, 128b621370aSMagnus Damm }; 129b621370aSMagnus Damm 130b621370aSMagnus Damm static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 131b621370aSMagnus Damm 132b621370aSMagnus Damm static struct clk_div_mult_table div4_table = { 133b621370aSMagnus Damm .divisors = divisors, 134b621370aSMagnus Damm .nr_divisors = ARRAY_SIZE(divisors), 135b621370aSMagnus Damm }; 136b621370aSMagnus Damm 137b621370aSMagnus Damm enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 138b621370aSMagnus Damm 139b621370aSMagnus Damm #define DIV4(_str, _reg, _bit, _mask, _flags) \ 140b621370aSMagnus Damm SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 141b621370aSMagnus Damm 142b621370aSMagnus Damm struct clk div4_clks[DIV4_NR] = { 143b621370aSMagnus Damm [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 144b621370aSMagnus Damm [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 145b621370aSMagnus Damm [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 146b621370aSMagnus Damm [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 147b621370aSMagnus Damm [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0), 148b621370aSMagnus Damm }; 149b621370aSMagnus Damm 150b621370aSMagnus Damm struct clk div6_clks[] = { 151b621370aSMagnus Damm SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), 152b621370aSMagnus Damm SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 153b621370aSMagnus Damm SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 154b621370aSMagnus Damm SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 155b621370aSMagnus Damm SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), 156b621370aSMagnus Damm }; 157b621370aSMagnus Damm 1586ba4a8f0SMagnus Damm #define R_CLK (&r_clk) 1596ba4a8f0SMagnus Damm #define P_CLK (&div4_clks[DIV4_P]) 1606ba4a8f0SMagnus Damm #define B_CLK (&div4_clks[DIV4_B]) 1616ba4a8f0SMagnus Damm #define I_CLK (&div4_clks[DIV4_I]) 1626ba4a8f0SMagnus Damm #define SH_CLK (&div4_clks[DIV4_SH]) 163b621370aSMagnus Damm 164b621370aSMagnus Damm static struct clk mstp_clks[] = { 1656ba4a8f0SMagnus Damm SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 1666ba4a8f0SMagnus Damm SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 1676ba4a8f0SMagnus Damm SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 1686ba4a8f0SMagnus Damm SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT), 1696ba4a8f0SMagnus Damm SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 1706ba4a8f0SMagnus Damm SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 1716ba4a8f0SMagnus Damm SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 1726ba4a8f0SMagnus Damm SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 1736ba4a8f0SMagnus Damm SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 1746ba4a8f0SMagnus Damm SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 1756ba4a8f0SMagnus Damm SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 1766ba4a8f0SMagnus Damm SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 1776ba4a8f0SMagnus Damm SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 1786ba4a8f0SMagnus Damm SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 1796ba4a8f0SMagnus Damm SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 1806ba4a8f0SMagnus Damm SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 1816ba4a8f0SMagnus Damm SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 1826ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 1836ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 1846ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 1856ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 1866ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 1876ba4a8f0SMagnus Damm SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 1886ba4a8f0SMagnus Damm SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 1896ba4a8f0SMagnus Damm SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 190b621370aSMagnus Damm 1916ba4a8f0SMagnus Damm SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 1926ba4a8f0SMagnus Damm SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 1936ba4a8f0SMagnus Damm SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0), 1946ba4a8f0SMagnus Damm SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0), 195b621370aSMagnus Damm 1966ba4a8f0SMagnus Damm SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0), 1976ba4a8f0SMagnus Damm SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0), 1986ba4a8f0SMagnus Damm SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0), 1996ba4a8f0SMagnus Damm SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 2006ba4a8f0SMagnus Damm SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 2016ba4a8f0SMagnus Damm SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 2026ba4a8f0SMagnus Damm SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0), 2036ba4a8f0SMagnus Damm SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0), 2046ba4a8f0SMagnus Damm SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 2056ba4a8f0SMagnus Damm SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 2066ba4a8f0SMagnus Damm SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 207cc58f597SMagnus Damm SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0), 2086ba4a8f0SMagnus Damm SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0), 2096ba4a8f0SMagnus Damm SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0), 2106ba4a8f0SMagnus Damm SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0), 2116ba4a8f0SMagnus Damm SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0), 212cc58f597SMagnus Damm SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 2136ba4a8f0SMagnus Damm SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 2146ba4a8f0SMagnus Damm SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0), 2156ba4a8f0SMagnus Damm SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0), 216cc58f597SMagnus Damm SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0), 217cc58f597SMagnus Damm SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 2186ba4a8f0SMagnus Damm SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 219b621370aSMagnus Damm }; 220b621370aSMagnus Damm 221b621370aSMagnus Damm int __init arch_clk_init(void) 222b621370aSMagnus Damm { 223b621370aSMagnus Damm int k, ret = 0; 224b621370aSMagnus Damm 225b621370aSMagnus Damm /* autodetect extal or fll configuration */ 226b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 227b621370aSMagnus Damm pll_clk.parent = &fll_clk; 228b621370aSMagnus Damm else 229b621370aSMagnus Damm pll_clk.parent = &extal_clk; 230b621370aSMagnus Damm 231b621370aSMagnus Damm for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 232b621370aSMagnus Damm ret = clk_register(main_clks[k]); 233b621370aSMagnus Damm 234b621370aSMagnus Damm if (!ret) 235b621370aSMagnus Damm ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 236b621370aSMagnus Damm 237b621370aSMagnus Damm if (!ret) 238b621370aSMagnus Damm ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 239b621370aSMagnus Damm 240b621370aSMagnus Damm if (!ret) 2416ba4a8f0SMagnus Damm ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 242b621370aSMagnus Damm 243b621370aSMagnus Damm return ret; 244b621370aSMagnus Damm } 245