1b621370aSMagnus Damm /* 2b621370aSMagnus Damm * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3b621370aSMagnus Damm * 4b621370aSMagnus Damm * SH7724 clock framework support 5b621370aSMagnus Damm * 6b621370aSMagnus Damm * Copyright (C) 2009 Magnus Damm 7b621370aSMagnus Damm * 8b621370aSMagnus Damm * This program is free software; you can redistribute it and/or modify 9b621370aSMagnus Damm * it under the terms of the GNU General Public License as published by 10b621370aSMagnus Damm * the Free Software Foundation; either version 2 of the License 11b621370aSMagnus Damm * 12b621370aSMagnus Damm * This program is distributed in the hope that it will be useful, 13b621370aSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b621370aSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b621370aSMagnus Damm * GNU General Public License for more details. 16b621370aSMagnus Damm * 17b621370aSMagnus Damm * You should have received a copy of the GNU General Public License 18b621370aSMagnus Damm * along with this program; if not, write to the Free Software 19b621370aSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b621370aSMagnus Damm */ 21b621370aSMagnus Damm #include <linux/init.h> 22b621370aSMagnus Damm #include <linux/kernel.h> 23b621370aSMagnus Damm #include <linux/io.h> 24f4cff0d0SPaul Mundt #include <linux/clk.h> 25f4cff0d0SPaul Mundt #include <asm/clkdev.h> 26b621370aSMagnus Damm #include <asm/clock.h> 276ba4a8f0SMagnus Damm #include <asm/hwblk.h> 286ba4a8f0SMagnus Damm #include <cpu/sh7724.h> 29b621370aSMagnus Damm 30b621370aSMagnus Damm /* SH7724 registers */ 31b621370aSMagnus Damm #define FRQCRA 0xa4150000 32b621370aSMagnus Damm #define FRQCRB 0xa4150004 33b621370aSMagnus Damm #define VCLKCR 0xa4150048 34b621370aSMagnus Damm #define FCLKACR 0xa4150008 35b621370aSMagnus Damm #define FCLKBCR 0xa415000c 36b621370aSMagnus Damm #define IRDACLKCR 0xa4150018 37b621370aSMagnus Damm #define PLLCR 0xa4150024 38b621370aSMagnus Damm #define SPUCLKCR 0xa415003c 39b621370aSMagnus Damm #define FLLFRQ 0xa4150050 40b621370aSMagnus Damm #define LSTATS 0xa4150060 41b621370aSMagnus Damm 42b621370aSMagnus Damm /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 43b621370aSMagnus Damm static struct clk r_clk = { 44b621370aSMagnus Damm .name = "rclk", 45b621370aSMagnus Damm .id = -1, 46b621370aSMagnus Damm .rate = 32768, 47b621370aSMagnus Damm }; 48b621370aSMagnus Damm 49b621370aSMagnus Damm /* 50b621370aSMagnus Damm * Default rate for the root input clock, reset this with clk_set_rate() 51b621370aSMagnus Damm * from the platform code. 52b621370aSMagnus Damm */ 53b621370aSMagnus Damm struct clk extal_clk = { 54b621370aSMagnus Damm .name = "extal", 55b621370aSMagnus Damm .id = -1, 56b621370aSMagnus Damm .rate = 33333333, 57b621370aSMagnus Damm }; 58b621370aSMagnus Damm 59b621370aSMagnus Damm /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 60b621370aSMagnus Damm static unsigned long fll_recalc(struct clk *clk) 61b621370aSMagnus Damm { 62b621370aSMagnus Damm unsigned long mult = 0; 63b621370aSMagnus Damm unsigned long div = 1; 64b621370aSMagnus Damm 65b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 66b621370aSMagnus Damm mult = __raw_readl(FLLFRQ) & 0x3ff; 67b621370aSMagnus Damm 68b621370aSMagnus Damm if (__raw_readl(FLLFRQ) & 0x4000) 69b621370aSMagnus Damm div = 2; 70b621370aSMagnus Damm 71b621370aSMagnus Damm return (clk->parent->rate * mult) / div; 72b621370aSMagnus Damm } 73b621370aSMagnus Damm 74b621370aSMagnus Damm static struct clk_ops fll_clk_ops = { 75b621370aSMagnus Damm .recalc = fll_recalc, 76b621370aSMagnus Damm }; 77b621370aSMagnus Damm 78b621370aSMagnus Damm static struct clk fll_clk = { 79b621370aSMagnus Damm .name = "fll_clk", 80b621370aSMagnus Damm .id = -1, 81b621370aSMagnus Damm .ops = &fll_clk_ops, 82b621370aSMagnus Damm .parent = &r_clk, 83b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 84b621370aSMagnus Damm }; 85b621370aSMagnus Damm 86b621370aSMagnus Damm static unsigned long pll_recalc(struct clk *clk) 87b621370aSMagnus Damm { 88b621370aSMagnus Damm unsigned long mult = 1; 89b621370aSMagnus Damm 90b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x4000) 91b621370aSMagnus Damm mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 92b621370aSMagnus Damm 93b621370aSMagnus Damm return clk->parent->rate * mult; 94b621370aSMagnus Damm } 95b621370aSMagnus Damm 96b621370aSMagnus Damm static struct clk_ops pll_clk_ops = { 97b621370aSMagnus Damm .recalc = pll_recalc, 98b621370aSMagnus Damm }; 99b621370aSMagnus Damm 100b621370aSMagnus Damm static struct clk pll_clk = { 101b621370aSMagnus Damm .name = "pll_clk", 102b621370aSMagnus Damm .id = -1, 103b621370aSMagnus Damm .ops = &pll_clk_ops, 104b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 105b621370aSMagnus Damm }; 106b621370aSMagnus Damm 107b621370aSMagnus Damm /* A fixed divide-by-3 block use by the div6 clocks */ 108b621370aSMagnus Damm static unsigned long div3_recalc(struct clk *clk) 109b621370aSMagnus Damm { 110b621370aSMagnus Damm return clk->parent->rate / 3; 111b621370aSMagnus Damm } 112b621370aSMagnus Damm 113b621370aSMagnus Damm static struct clk_ops div3_clk_ops = { 114b621370aSMagnus Damm .recalc = div3_recalc, 115b621370aSMagnus Damm }; 116b621370aSMagnus Damm 117b621370aSMagnus Damm static struct clk div3_clk = { 118b621370aSMagnus Damm .name = "div3_clk", 119b621370aSMagnus Damm .id = -1, 120b621370aSMagnus Damm .ops = &div3_clk_ops, 121b621370aSMagnus Damm .parent = &pll_clk, 122b621370aSMagnus Damm }; 123b621370aSMagnus Damm 124b621370aSMagnus Damm struct clk *main_clks[] = { 125b621370aSMagnus Damm &r_clk, 126b621370aSMagnus Damm &extal_clk, 127b621370aSMagnus Damm &fll_clk, 128b621370aSMagnus Damm &pll_clk, 129b621370aSMagnus Damm &div3_clk, 130b621370aSMagnus Damm }; 131b621370aSMagnus Damm 1327be85c6eSMagnus Damm static void div4_kick(struct clk *clk) 1337be85c6eSMagnus Damm { 1347be85c6eSMagnus Damm unsigned long value; 1357be85c6eSMagnus Damm 1367be85c6eSMagnus Damm /* set KICK bit in FRQCRA to update hardware setting */ 1377be85c6eSMagnus Damm value = __raw_readl(FRQCRA); 1387be85c6eSMagnus Damm value |= (1 << 31); 1397be85c6eSMagnus Damm __raw_writel(value, FRQCRA); 1407be85c6eSMagnus Damm } 1417be85c6eSMagnus Damm 142b2ea8b42SKuninori Morimoto static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 143b621370aSMagnus Damm 1440a5f337eSMagnus Damm static struct clk_div_mult_table div4_div_mult_table = { 145b621370aSMagnus Damm .divisors = divisors, 146b621370aSMagnus Damm .nr_divisors = ARRAY_SIZE(divisors), 147b621370aSMagnus Damm }; 148b621370aSMagnus Damm 1490a5f337eSMagnus Damm static struct clk_div4_table div4_table = { 1500a5f337eSMagnus Damm .div_mult_table = &div4_div_mult_table, 1517be85c6eSMagnus Damm .kick = div4_kick, 1520a5f337eSMagnus Damm }; 1530a5f337eSMagnus Damm 154b621370aSMagnus Damm enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 155b621370aSMagnus Damm 156b621370aSMagnus Damm #define DIV4(_str, _reg, _bit, _mask, _flags) \ 157b621370aSMagnus Damm SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 158b621370aSMagnus Damm 159b621370aSMagnus Damm struct clk div4_clks[DIV4_NR] = { 160b621370aSMagnus Damm [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 161b621370aSMagnus Damm [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 162b621370aSMagnus Damm [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 163b621370aSMagnus Damm [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 1646f26d19fSMagnus Damm [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 165b621370aSMagnus Damm }; 166b621370aSMagnus Damm 167098ec49bSMagnus Damm enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 168098ec49bSMagnus Damm 169098ec49bSMagnus Damm struct clk div6_clks[DIV6_NR] = { 1709e1985e1SMagnus Damm [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 1719e1985e1SMagnus Damm [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), 1729e1985e1SMagnus Damm [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), 1739e1985e1SMagnus Damm [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 1749e1985e1SMagnus Damm [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 175b621370aSMagnus Damm }; 176b621370aSMagnus Damm 177f3d51e13SMagnus Damm static struct clk mstp_clks[HWBLK_NR] = { 17808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 17908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 18008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 18108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 18208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 18308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 18408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 18508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 18608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 18708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 18808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 18908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 19008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 19108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 19208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 19308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 19408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 19508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 19608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 19708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 19808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 19908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 20008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 20108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 20208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 203b621370aSMagnus Damm 20408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 20508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 20608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 20708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 208b621370aSMagnus Damm 20908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 21008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 21108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 21208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 21308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 21408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 21508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 21608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 21708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 21808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 21908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 22008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 22108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 22208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 22308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 22408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 22508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 22608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 22708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 22808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 22908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 23008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 23108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 232b621370aSMagnus Damm }; 233b621370aSMagnus Damm 234fd30401bSMagnus Damm #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 235fd30401bSMagnus Damm 236f4cff0d0SPaul Mundt static struct clk_lookup lookups[] = { 237098ec49bSMagnus Damm /* DIV6 clocks */ 238098ec49bSMagnus Damm CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 239098ec49bSMagnus Damm CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 240098ec49bSMagnus Damm CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), 241098ec49bSMagnus Damm CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 242098ec49bSMagnus Damm CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 243098ec49bSMagnus Damm 244fd30401bSMagnus Damm /* MSTP clocks */ 245fd30401bSMagnus Damm CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 246fd30401bSMagnus Damm CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 247fd30401bSMagnus Damm CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 248fd30401bSMagnus Damm CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), 249fd30401bSMagnus Damm CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 250fd30401bSMagnus Damm CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 251fd30401bSMagnus Damm CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 252fd30401bSMagnus Damm CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 253fd30401bSMagnus Damm CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 254fd30401bSMagnus Damm CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 255fd30401bSMagnus Damm CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 256fd30401bSMagnus Damm CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 257f4cff0d0SPaul Mundt { 258f4cff0d0SPaul Mundt /* TMU0 */ 259f4cff0d0SPaul Mundt .dev_id = "sh_tmu.0", 260f4cff0d0SPaul Mundt .con_id = "tmu_fck", 261f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 262f4cff0d0SPaul Mundt }, { 263f4cff0d0SPaul Mundt /* TMU1 */ 264f4cff0d0SPaul Mundt .dev_id = "sh_tmu.1", 265f4cff0d0SPaul Mundt .con_id = "tmu_fck", 266f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 267f4cff0d0SPaul Mundt }, { 268f4cff0d0SPaul Mundt /* TMU2 */ 269f4cff0d0SPaul Mundt .dev_id = "sh_tmu.2", 270f4cff0d0SPaul Mundt .con_id = "tmu_fck", 271f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 272f4cff0d0SPaul Mundt }, { 273f4cff0d0SPaul Mundt /* TMU3 */ 274f4cff0d0SPaul Mundt .dev_id = "sh_tmu.3", 275f4cff0d0SPaul Mundt .con_id = "tmu_fck", 276f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 277fd30401bSMagnus Damm }, 278fd30401bSMagnus Damm CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 279fd30401bSMagnus Damm CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 280fd30401bSMagnus Damm CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 281fd30401bSMagnus Damm { 282f4cff0d0SPaul Mundt /* TMU4 */ 283f4cff0d0SPaul Mundt .dev_id = "sh_tmu.4", 284f4cff0d0SPaul Mundt .con_id = "tmu_fck", 285f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 286f4cff0d0SPaul Mundt }, { 287f4cff0d0SPaul Mundt /* TMU5 */ 288f4cff0d0SPaul Mundt .dev_id = "sh_tmu.5", 289f4cff0d0SPaul Mundt .con_id = "tmu_fck", 290f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 291e4e06697SMagnus Damm }, { 292e4e06697SMagnus Damm /* SCIF0 */ 293e4e06697SMagnus Damm .dev_id = "sh-sci.0", 294e4e06697SMagnus Damm .con_id = "sci_fck", 295e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF0], 296e4e06697SMagnus Damm }, { 297e4e06697SMagnus Damm /* SCIF1 */ 298e4e06697SMagnus Damm .dev_id = "sh-sci.1", 299e4e06697SMagnus Damm .con_id = "sci_fck", 300e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF1], 301e4e06697SMagnus Damm }, { 302e4e06697SMagnus Damm /* SCIF2 */ 303e4e06697SMagnus Damm .dev_id = "sh-sci.2", 304e4e06697SMagnus Damm .con_id = "sci_fck", 305e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF2], 306e4e06697SMagnus Damm }, { 307e4e06697SMagnus Damm /* SCIF3 */ 308e4e06697SMagnus Damm .dev_id = "sh-sci.3", 309e4e06697SMagnus Damm .con_id = "sci_fck", 310e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF3], 311e4e06697SMagnus Damm }, { 312e4e06697SMagnus Damm /* SCIF4 */ 313e4e06697SMagnus Damm .dev_id = "sh-sci.4", 314e4e06697SMagnus Damm .con_id = "sci_fck", 315e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF4], 316e4e06697SMagnus Damm }, { 317e4e06697SMagnus Damm /* SCIF5 */ 318e4e06697SMagnus Damm .dev_id = "sh-sci.5", 319e4e06697SMagnus Damm .con_id = "sci_fck", 320e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF5], 321f4cff0d0SPaul Mundt }, 322fd30401bSMagnus Damm CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 323fd30401bSMagnus Damm CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 324fd30401bSMagnus Damm CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 325fd30401bSMagnus Damm CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 326fd30401bSMagnus Damm CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]), 327fd30401bSMagnus Damm CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]), 328fd30401bSMagnus Damm CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 329fd30401bSMagnus Damm CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 330fd30401bSMagnus Damm CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 331fd30401bSMagnus Damm CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 332fd30401bSMagnus Damm CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 333fd30401bSMagnus Damm CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 334fd30401bSMagnus Damm CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 335fd30401bSMagnus Damm CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 336fd30401bSMagnus Damm CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 337fd30401bSMagnus Damm CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 338fd30401bSMagnus Damm CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 339fd30401bSMagnus Damm CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 340fd30401bSMagnus Damm CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 341fd30401bSMagnus Damm CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 342fd30401bSMagnus Damm CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 343fd30401bSMagnus Damm CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 344fd30401bSMagnus Damm CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 345fd30401bSMagnus Damm CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 346fd30401bSMagnus Damm CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 347fd30401bSMagnus Damm CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 348fd30401bSMagnus Damm CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 349fd30401bSMagnus Damm CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 350fd30401bSMagnus Damm CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 351f4cff0d0SPaul Mundt }; 352f4cff0d0SPaul Mundt 353b621370aSMagnus Damm int __init arch_clk_init(void) 354b621370aSMagnus Damm { 355b621370aSMagnus Damm int k, ret = 0; 356b621370aSMagnus Damm 357b621370aSMagnus Damm /* autodetect extal or fll configuration */ 358b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 359b621370aSMagnus Damm pll_clk.parent = &fll_clk; 360b621370aSMagnus Damm else 361b621370aSMagnus Damm pll_clk.parent = &extal_clk; 362b621370aSMagnus Damm 363b621370aSMagnus Damm for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 364b621370aSMagnus Damm ret = clk_register(main_clks[k]); 365b621370aSMagnus Damm 366f4cff0d0SPaul Mundt clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 367f4cff0d0SPaul Mundt 368b621370aSMagnus Damm if (!ret) 369b621370aSMagnus Damm ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 370b621370aSMagnus Damm 371b621370aSMagnus Damm if (!ret) 372098ec49bSMagnus Damm ret = sh_clk_div6_register(div6_clks, DIV6_NR); 373b621370aSMagnus Damm 374b621370aSMagnus Damm if (!ret) 375f3d51e13SMagnus Damm ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 376b621370aSMagnus Damm 377b621370aSMagnus Damm return ret; 378b621370aSMagnus Damm } 379