1b621370aSMagnus Damm /* 2b621370aSMagnus Damm * arch/sh/kernel/cpu/sh4a/clock-sh7724.c 3b621370aSMagnus Damm * 4b621370aSMagnus Damm * SH7724 clock framework support 5b621370aSMagnus Damm * 6b621370aSMagnus Damm * Copyright (C) 2009 Magnus Damm 7b621370aSMagnus Damm * 8b621370aSMagnus Damm * This program is free software; you can redistribute it and/or modify 9b621370aSMagnus Damm * it under the terms of the GNU General Public License as published by 10b621370aSMagnus Damm * the Free Software Foundation; either version 2 of the License 11b621370aSMagnus Damm * 12b621370aSMagnus Damm * This program is distributed in the hope that it will be useful, 13b621370aSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b621370aSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b621370aSMagnus Damm * GNU General Public License for more details. 16b621370aSMagnus Damm * 17b621370aSMagnus Damm * You should have received a copy of the GNU General Public License 18b621370aSMagnus Damm * along with this program; if not, write to the Free Software 19b621370aSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20b621370aSMagnus Damm */ 21b621370aSMagnus Damm #include <linux/init.h> 22b621370aSMagnus Damm #include <linux/kernel.h> 23b621370aSMagnus Damm #include <linux/io.h> 24f4cff0d0SPaul Mundt #include <linux/clk.h> 256d803ba7SJean-Christop PLAGNIOL-VILLARD #include <linux/clkdev.h> 26b621370aSMagnus Damm #include <asm/clock.h> 276ba4a8f0SMagnus Damm #include <asm/hwblk.h> 286ba4a8f0SMagnus Damm #include <cpu/sh7724.h> 29b621370aSMagnus Damm 30b621370aSMagnus Damm /* SH7724 registers */ 31b621370aSMagnus Damm #define FRQCRA 0xa4150000 32b621370aSMagnus Damm #define FRQCRB 0xa4150004 33b621370aSMagnus Damm #define VCLKCR 0xa4150048 34b621370aSMagnus Damm #define FCLKACR 0xa4150008 35b621370aSMagnus Damm #define FCLKBCR 0xa415000c 36b621370aSMagnus Damm #define IRDACLKCR 0xa4150018 37b621370aSMagnus Damm #define PLLCR 0xa4150024 38b621370aSMagnus Damm #define SPUCLKCR 0xa415003c 39b621370aSMagnus Damm #define FLLFRQ 0xa4150050 40b621370aSMagnus Damm #define LSTATS 0xa4150060 41b621370aSMagnus Damm 42b621370aSMagnus Damm /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 43b621370aSMagnus Damm static struct clk r_clk = { 44b621370aSMagnus Damm .rate = 32768, 45b621370aSMagnus Damm }; 46b621370aSMagnus Damm 47b621370aSMagnus Damm /* 48b621370aSMagnus Damm * Default rate for the root input clock, reset this with clk_set_rate() 49b621370aSMagnus Damm * from the platform code. 50b621370aSMagnus Damm */ 51b621370aSMagnus Damm struct clk extal_clk = { 52b621370aSMagnus Damm .rate = 33333333, 53b621370aSMagnus Damm }; 54b621370aSMagnus Damm 55b621370aSMagnus Damm /* The fll multiplies the 32khz r_clk, may be used instead of extal */ 56b621370aSMagnus Damm static unsigned long fll_recalc(struct clk *clk) 57b621370aSMagnus Damm { 58b621370aSMagnus Damm unsigned long mult = 0; 59b621370aSMagnus Damm unsigned long div = 1; 60b621370aSMagnus Damm 61b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 62b621370aSMagnus Damm mult = __raw_readl(FLLFRQ) & 0x3ff; 63b621370aSMagnus Damm 64b621370aSMagnus Damm if (__raw_readl(FLLFRQ) & 0x4000) 65b621370aSMagnus Damm div = 2; 66b621370aSMagnus Damm 67b621370aSMagnus Damm return (clk->parent->rate * mult) / div; 68b621370aSMagnus Damm } 69b621370aSMagnus Damm 70b621370aSMagnus Damm static struct clk_ops fll_clk_ops = { 71b621370aSMagnus Damm .recalc = fll_recalc, 72b621370aSMagnus Damm }; 73b621370aSMagnus Damm 74b621370aSMagnus Damm static struct clk fll_clk = { 75b621370aSMagnus Damm .ops = &fll_clk_ops, 76b621370aSMagnus Damm .parent = &r_clk, 77b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 78b621370aSMagnus Damm }; 79b621370aSMagnus Damm 80b621370aSMagnus Damm static unsigned long pll_recalc(struct clk *clk) 81b621370aSMagnus Damm { 82b621370aSMagnus Damm unsigned long mult = 1; 83b621370aSMagnus Damm 84b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x4000) 85b621370aSMagnus Damm mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; 86b621370aSMagnus Damm 87b621370aSMagnus Damm return clk->parent->rate * mult; 88b621370aSMagnus Damm } 89b621370aSMagnus Damm 90b621370aSMagnus Damm static struct clk_ops pll_clk_ops = { 91b621370aSMagnus Damm .recalc = pll_recalc, 92b621370aSMagnus Damm }; 93b621370aSMagnus Damm 94b621370aSMagnus Damm static struct clk pll_clk = { 95b621370aSMagnus Damm .ops = &pll_clk_ops, 96b621370aSMagnus Damm .flags = CLK_ENABLE_ON_INIT, 97b621370aSMagnus Damm }; 98b621370aSMagnus Damm 99b621370aSMagnus Damm /* A fixed divide-by-3 block use by the div6 clocks */ 100b621370aSMagnus Damm static unsigned long div3_recalc(struct clk *clk) 101b621370aSMagnus Damm { 102b621370aSMagnus Damm return clk->parent->rate / 3; 103b621370aSMagnus Damm } 104b621370aSMagnus Damm 105b621370aSMagnus Damm static struct clk_ops div3_clk_ops = { 106b621370aSMagnus Damm .recalc = div3_recalc, 107b621370aSMagnus Damm }; 108b621370aSMagnus Damm 109b621370aSMagnus Damm static struct clk div3_clk = { 110b621370aSMagnus Damm .ops = &div3_clk_ops, 111b621370aSMagnus Damm .parent = &pll_clk, 112b621370aSMagnus Damm }; 113b621370aSMagnus Damm 114b621370aSMagnus Damm struct clk *main_clks[] = { 115b621370aSMagnus Damm &r_clk, 116b621370aSMagnus Damm &extal_clk, 117b621370aSMagnus Damm &fll_clk, 118b621370aSMagnus Damm &pll_clk, 119b621370aSMagnus Damm &div3_clk, 120b621370aSMagnus Damm }; 121b621370aSMagnus Damm 1227be85c6eSMagnus Damm static void div4_kick(struct clk *clk) 1237be85c6eSMagnus Damm { 1247be85c6eSMagnus Damm unsigned long value; 1257be85c6eSMagnus Damm 1267be85c6eSMagnus Damm /* set KICK bit in FRQCRA to update hardware setting */ 1277be85c6eSMagnus Damm value = __raw_readl(FRQCRA); 1287be85c6eSMagnus Damm value |= (1 << 31); 1297be85c6eSMagnus Damm __raw_writel(value, FRQCRA); 1307be85c6eSMagnus Damm } 1317be85c6eSMagnus Damm 132b2ea8b42SKuninori Morimoto static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 133b621370aSMagnus Damm 1340a5f337eSMagnus Damm static struct clk_div_mult_table div4_div_mult_table = { 135b621370aSMagnus Damm .divisors = divisors, 136b621370aSMagnus Damm .nr_divisors = ARRAY_SIZE(divisors), 137b621370aSMagnus Damm }; 138b621370aSMagnus Damm 1390a5f337eSMagnus Damm static struct clk_div4_table div4_table = { 1400a5f337eSMagnus Damm .div_mult_table = &div4_div_mult_table, 1417be85c6eSMagnus Damm .kick = div4_kick, 1420a5f337eSMagnus Damm }; 1430a5f337eSMagnus Damm 144b621370aSMagnus Damm enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 145b621370aSMagnus Damm 146914ebf0bSMagnus Damm #define DIV4(_reg, _bit, _mask, _flags) \ 147914ebf0bSMagnus Damm SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 148b621370aSMagnus Damm 149b621370aSMagnus Damm struct clk div4_clks[DIV4_NR] = { 150914ebf0bSMagnus Damm [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 151914ebf0bSMagnus Damm [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 152914ebf0bSMagnus Damm [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 153914ebf0bSMagnus Damm [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), 154914ebf0bSMagnus Damm [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 155b621370aSMagnus Damm }; 156b621370aSMagnus Damm 157098ec49bSMagnus Damm enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 158098ec49bSMagnus Damm 159098ec49bSMagnus Damm struct clk div6_clks[DIV6_NR] = { 1609e1985e1SMagnus Damm [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 1619e1985e1SMagnus Damm [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), 1629e1985e1SMagnus Damm [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), 1639e1985e1SMagnus Damm [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 1649e1985e1SMagnus Damm [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 165b621370aSMagnus Damm }; 166b621370aSMagnus Damm 167f3d51e13SMagnus Damm static struct clk mstp_clks[HWBLK_NR] = { 16808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 16908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 17008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 17108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 17208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 17308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 17408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 17508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 17608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 17708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 17808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 17908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 18008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 18108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 18208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 18308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 18408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 18508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 18608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 18708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 18808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 18908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 19008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 19108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 19208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 193b621370aSMagnus Damm 19408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 19508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 19608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 19708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 198b621370aSMagnus Damm 19908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 20008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 20108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 20208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 20308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 20408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 20508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 20608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 20708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 20808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 20908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 21008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 21108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 21208134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 21308134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 21408134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 21508134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 21608134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 21708134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 21808134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 21908134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 22008134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 22108134c3cSMagnus Damm SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 222b621370aSMagnus Damm }; 223b621370aSMagnus Damm 224fd30401bSMagnus Damm #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 225fd30401bSMagnus Damm 226f4cff0d0SPaul Mundt static struct clk_lookup lookups[] = { 227b3f9f630SMagnus Damm /* main clocks */ 228b3f9f630SMagnus Damm CLKDEV_CON_ID("rclk", &r_clk), 229b3f9f630SMagnus Damm CLKDEV_CON_ID("extal", &extal_clk), 230b3f9f630SMagnus Damm CLKDEV_CON_ID("fll_clk", &fll_clk), 231b3f9f630SMagnus Damm CLKDEV_CON_ID("pll_clk", &pll_clk), 232b3f9f630SMagnus Damm CLKDEV_CON_ID("div3_clk", &div3_clk), 233b3f9f630SMagnus Damm 2341c4cde2eSMagnus Damm /* DIV4 clocks */ 2351c4cde2eSMagnus Damm CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 2361c4cde2eSMagnus Damm CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 2371c4cde2eSMagnus Damm CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 2381c4cde2eSMagnus Damm CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 2391c4cde2eSMagnus Damm CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), 2401c4cde2eSMagnus Damm 241098ec49bSMagnus Damm /* DIV6 clocks */ 242098ec49bSMagnus Damm CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 243098ec49bSMagnus Damm CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 244098ec49bSMagnus Damm CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), 245098ec49bSMagnus Damm CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 246098ec49bSMagnus Damm CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 247098ec49bSMagnus Damm 248fd30401bSMagnus Damm /* MSTP clocks */ 249fd30401bSMagnus Damm CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 250fd30401bSMagnus Damm CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 251fd30401bSMagnus Damm CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 252fd30401bSMagnus Damm CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), 253fd30401bSMagnus Damm CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 254fd30401bSMagnus Damm CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 255fd30401bSMagnus Damm CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 256fd30401bSMagnus Damm CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 257fd30401bSMagnus Damm CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 258fd30401bSMagnus Damm CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 259fd30401bSMagnus Damm CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 260fd30401bSMagnus Damm CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 261f4cff0d0SPaul Mundt { 262f4cff0d0SPaul Mundt /* TMU0 */ 263f4cff0d0SPaul Mundt .dev_id = "sh_tmu.0", 264f4cff0d0SPaul Mundt .con_id = "tmu_fck", 265f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 266f4cff0d0SPaul Mundt }, { 267f4cff0d0SPaul Mundt /* TMU1 */ 268f4cff0d0SPaul Mundt .dev_id = "sh_tmu.1", 269f4cff0d0SPaul Mundt .con_id = "tmu_fck", 270f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 271f4cff0d0SPaul Mundt }, { 272f4cff0d0SPaul Mundt /* TMU2 */ 273f4cff0d0SPaul Mundt .dev_id = "sh_tmu.2", 274f4cff0d0SPaul Mundt .con_id = "tmu_fck", 275f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU0], 276f4cff0d0SPaul Mundt }, { 277f4cff0d0SPaul Mundt /* TMU3 */ 278f4cff0d0SPaul Mundt .dev_id = "sh_tmu.3", 279f4cff0d0SPaul Mundt .con_id = "tmu_fck", 280f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 281fd30401bSMagnus Damm }, 282fd30401bSMagnus Damm CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 283fd30401bSMagnus Damm CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 284fd30401bSMagnus Damm CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 285fd30401bSMagnus Damm { 286f4cff0d0SPaul Mundt /* TMU4 */ 287f4cff0d0SPaul Mundt .dev_id = "sh_tmu.4", 288f4cff0d0SPaul Mundt .con_id = "tmu_fck", 289f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 290f4cff0d0SPaul Mundt }, { 291f4cff0d0SPaul Mundt /* TMU5 */ 292f4cff0d0SPaul Mundt .dev_id = "sh_tmu.5", 293f4cff0d0SPaul Mundt .con_id = "tmu_fck", 294f3d51e13SMagnus Damm .clk = &mstp_clks[HWBLK_TMU1], 295e4e06697SMagnus Damm }, { 296e4e06697SMagnus Damm /* SCIF0 */ 297e4e06697SMagnus Damm .dev_id = "sh-sci.0", 298e4e06697SMagnus Damm .con_id = "sci_fck", 299e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF0], 300e4e06697SMagnus Damm }, { 301e4e06697SMagnus Damm /* SCIF1 */ 302e4e06697SMagnus Damm .dev_id = "sh-sci.1", 303e4e06697SMagnus Damm .con_id = "sci_fck", 304e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF1], 305e4e06697SMagnus Damm }, { 306e4e06697SMagnus Damm /* SCIF2 */ 307e4e06697SMagnus Damm .dev_id = "sh-sci.2", 308e4e06697SMagnus Damm .con_id = "sci_fck", 309e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF2], 310e4e06697SMagnus Damm }, { 311e4e06697SMagnus Damm /* SCIF3 */ 312e4e06697SMagnus Damm .dev_id = "sh-sci.3", 313e4e06697SMagnus Damm .con_id = "sci_fck", 314e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF3], 315e4e06697SMagnus Damm }, { 316e4e06697SMagnus Damm /* SCIF4 */ 317e4e06697SMagnus Damm .dev_id = "sh-sci.4", 318e4e06697SMagnus Damm .con_id = "sci_fck", 319e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF4], 320e4e06697SMagnus Damm }, { 321e4e06697SMagnus Damm /* SCIF5 */ 322e4e06697SMagnus Damm .dev_id = "sh-sci.5", 323e4e06697SMagnus Damm .con_id = "sci_fck", 324e4e06697SMagnus Damm .clk = &mstp_clks[HWBLK_SCIF5], 325f4cff0d0SPaul Mundt }, 326fd30401bSMagnus Damm CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 327fd30401bSMagnus Damm CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 328fd30401bSMagnus Damm CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 329fd30401bSMagnus Damm CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 330fd30401bSMagnus Damm CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]), 331fd30401bSMagnus Damm CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]), 332fd30401bSMagnus Damm CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 333fd30401bSMagnus Damm CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 334fd30401bSMagnus Damm CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 335fd30401bSMagnus Damm CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 336fd30401bSMagnus Damm CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 337fd30401bSMagnus Damm CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 338fd30401bSMagnus Damm CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 339fd30401bSMagnus Damm CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 340fd30401bSMagnus Damm CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 341fd30401bSMagnus Damm CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 342fd30401bSMagnus Damm CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 343fd30401bSMagnus Damm CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 344fd30401bSMagnus Damm CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 345fd30401bSMagnus Damm CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 346fd30401bSMagnus Damm CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 347fd30401bSMagnus Damm CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 348fd30401bSMagnus Damm CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 349fd30401bSMagnus Damm CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 350fd30401bSMagnus Damm CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 351fd30401bSMagnus Damm CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 352fd30401bSMagnus Damm CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 353fd30401bSMagnus Damm CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 354fd30401bSMagnus Damm CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 355f4cff0d0SPaul Mundt }; 356f4cff0d0SPaul Mundt 357b621370aSMagnus Damm int __init arch_clk_init(void) 358b621370aSMagnus Damm { 359b621370aSMagnus Damm int k, ret = 0; 360b621370aSMagnus Damm 361b621370aSMagnus Damm /* autodetect extal or fll configuration */ 362b621370aSMagnus Damm if (__raw_readl(PLLCR) & 0x1000) 363b621370aSMagnus Damm pll_clk.parent = &fll_clk; 364b621370aSMagnus Damm else 365b621370aSMagnus Damm pll_clk.parent = &extal_clk; 366b621370aSMagnus Damm 367b621370aSMagnus Damm for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 368b621370aSMagnus Damm ret = clk_register(main_clks[k]); 369b621370aSMagnus Damm 370f4cff0d0SPaul Mundt clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 371f4cff0d0SPaul Mundt 372b621370aSMagnus Damm if (!ret) 373b621370aSMagnus Damm ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 374b621370aSMagnus Damm 375b621370aSMagnus Damm if (!ret) 376098ec49bSMagnus Damm ret = sh_clk_div6_register(div6_clks, DIV6_NR); 377b621370aSMagnus Damm 378b621370aSMagnus Damm if (!ret) 379f3d51e13SMagnus Damm ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 380b621370aSMagnus Damm 381b621370aSMagnus Damm return ret; 382b621370aSMagnus Damm } 383