1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c 3 * 4 * SH7723 clock framework support 5 * 6 * Copyright (C) 2009 Magnus Damm 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/clk.h> 25 #include <asm/clkdev.h> 26 #include <asm/clock.h> 27 #include <asm/hwblk.h> 28 #include <cpu/sh7723.h> 29 30 /* SH7723 registers */ 31 #define FRQCR 0xa4150000 32 #define VCLKCR 0xa4150004 33 #define SCLKACR 0xa4150008 34 #define SCLKBCR 0xa415000c 35 #define IRDACLKCR 0xa4150018 36 #define PLLCR 0xa4150024 37 #define DLLFRQ 0xa4150050 38 39 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 40 static struct clk r_clk = { 41 .rate = 32768, 42 }; 43 44 /* 45 * Default rate for the root input clock, reset this with clk_set_rate() 46 * from the platform code. 47 */ 48 struct clk extal_clk = { 49 .rate = 33333333, 50 }; 51 52 /* The dll multiplies the 32khz r_clk, may be used instead of extal */ 53 static unsigned long dll_recalc(struct clk *clk) 54 { 55 unsigned long mult; 56 57 if (__raw_readl(PLLCR) & 0x1000) 58 mult = __raw_readl(DLLFRQ); 59 else 60 mult = 0; 61 62 return clk->parent->rate * mult; 63 } 64 65 static struct clk_ops dll_clk_ops = { 66 .recalc = dll_recalc, 67 }; 68 69 static struct clk dll_clk = { 70 .ops = &dll_clk_ops, 71 .parent = &r_clk, 72 .flags = CLK_ENABLE_ON_INIT, 73 }; 74 75 static unsigned long pll_recalc(struct clk *clk) 76 { 77 unsigned long mult = 1; 78 unsigned long div = 1; 79 80 if (__raw_readl(PLLCR) & 0x4000) 81 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); 82 else 83 div = 2; 84 85 return (clk->parent->rate * mult) / div; 86 } 87 88 static struct clk_ops pll_clk_ops = { 89 .recalc = pll_recalc, 90 }; 91 92 static struct clk pll_clk = { 93 .ops = &pll_clk_ops, 94 .flags = CLK_ENABLE_ON_INIT, 95 }; 96 97 struct clk *main_clks[] = { 98 &r_clk, 99 &extal_clk, 100 &dll_clk, 101 &pll_clk, 102 }; 103 104 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 105 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 106 107 static struct clk_div_mult_table div4_div_mult_table = { 108 .divisors = divisors, 109 .nr_divisors = ARRAY_SIZE(divisors), 110 .multipliers = multipliers, 111 .nr_multipliers = ARRAY_SIZE(multipliers), 112 }; 113 114 static struct clk_div4_table div4_table = { 115 .div_mult_table = &div4_div_mult_table, 116 }; 117 118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 119 120 #define DIV4(_reg, _bit, _mask, _flags) \ 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 122 123 struct clk div4_clks[DIV4_NR] = { 124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), 130 }; 131 132 enum { DIV4_IRDA, DIV4_ENABLE_NR }; 133 134 struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), 136 }; 137 138 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 139 140 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), 142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0), 143 }; 144 enum { DIV6_V, DIV6_NR }; 145 146 struct clk div6_clks[DIV6_NR] = { 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 148 }; 149 150 static struct clk mstp_clks[] = { 151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0), 178 179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 181 182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0), 183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0), 184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0), 192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0), 195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0), 199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 201 }; 202 203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 204 205 static struct clk_lookup lookups[] = { 206 /* main clocks */ 207 CLKDEV_CON_ID("rclk", &r_clk), 208 CLKDEV_CON_ID("extal", &extal_clk), 209 CLKDEV_CON_ID("dll_clk", &dll_clk), 210 CLKDEV_CON_ID("pll_clk", &pll_clk), 211 212 /* DIV4 clocks */ 213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 217 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), 218 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 219 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), 220 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), 221 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), 222 223 /* DIV6 clocks */ 224 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 225 226 /* MSTP clocks */ 227 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), 228 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), 229 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), 230 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 231 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 232 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 233 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 234 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 235 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 236 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 237 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 238 { 239 /* TMU0 */ 240 .dev_id = "sh_tmu.0", 241 .con_id = "tmu_fck", 242 .clk = &mstp_clks[HWBLK_TMU0], 243 }, { 244 /* TMU1 */ 245 .dev_id = "sh_tmu.1", 246 .con_id = "tmu_fck", 247 .clk = &mstp_clks[HWBLK_TMU0], 248 }, { 249 /* TMU2 */ 250 .dev_id = "sh_tmu.2", 251 .con_id = "tmu_fck", 252 .clk = &mstp_clks[HWBLK_TMU0], 253 }, 254 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 255 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 256 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 257 { 258 /* TMU3 */ 259 .dev_id = "sh_tmu.3", 260 .con_id = "tmu_fck", 261 .clk = &mstp_clks[HWBLK_TMU1], 262 }, { 263 /* TMU4 */ 264 .dev_id = "sh_tmu.4", 265 .con_id = "tmu_fck", 266 .clk = &mstp_clks[HWBLK_TMU1], 267 }, { 268 /* TMU5 */ 269 .dev_id = "sh_tmu.5", 270 .con_id = "tmu_fck", 271 .clk = &mstp_clks[HWBLK_TMU1], 272 }, 273 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 274 { 275 /* SCIF0 */ 276 .dev_id = "sh-sci.0", 277 .con_id = "sci_fck", 278 .clk = &mstp_clks[HWBLK_SCIF0], 279 }, { 280 /* SCIF1 */ 281 .dev_id = "sh-sci.1", 282 .con_id = "sci_fck", 283 .clk = &mstp_clks[HWBLK_SCIF1], 284 }, { 285 /* SCIF2 */ 286 .dev_id = "sh-sci.2", 287 .con_id = "sci_fck", 288 .clk = &mstp_clks[HWBLK_SCIF2], 289 }, { 290 /* SCIF3 */ 291 .dev_id = "sh-sci.3", 292 .con_id = "sci_fck", 293 .clk = &mstp_clks[HWBLK_SCIF3], 294 }, { 295 /* SCIF4 */ 296 .dev_id = "sh-sci.4", 297 .con_id = "sci_fck", 298 .clk = &mstp_clks[HWBLK_SCIF4], 299 }, { 300 /* SCIF5 */ 301 .dev_id = "sh-sci.5", 302 .con_id = "sci_fck", 303 .clk = &mstp_clks[HWBLK_SCIF5], 304 }, 305 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 306 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 307 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]), 308 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]), 309 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 310 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 311 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]), 312 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 313 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 314 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 315 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 316 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 317 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 318 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 319 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 320 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 321 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 322 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 323 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 324 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 325 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 326 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 327 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 328 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 329 }; 330 331 int __init arch_clk_init(void) 332 { 333 int k, ret = 0; 334 335 /* autodetect extal or dll configuration */ 336 if (__raw_readl(PLLCR) & 0x1000) 337 pll_clk.parent = &dll_clk; 338 else 339 pll_clk.parent = &extal_clk; 340 341 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 342 ret |= clk_register(main_clks[k]); 343 344 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 345 346 if (!ret) 347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 348 349 if (!ret) 350 ret = sh_clk_div4_enable_register(div4_enable_clks, 351 DIV4_ENABLE_NR, &div4_table); 352 353 if (!ret) 354 ret = sh_clk_div4_reparent_register(div4_reparent_clks, 355 DIV4_REPARENT_NR, &div4_table); 356 357 if (!ret) 358 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 359 360 if (!ret) 361 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 362 363 return ret; 364 } 365