1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c 3 * 4 * SH7722 & SH7366 support for the clock framework 5 * 6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc 7 * Based on code for sh7343 by Paul Mundt 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/io.h> 16 #include <linux/errno.h> 17 #include <asm/clock.h> 18 #include <asm/freq.h> 19 20 #define N (-1) 21 #define NM (-2) 22 #define ROUND_NEAREST 0 23 #define ROUND_DOWN -1 24 #define ROUND_UP +1 25 26 static int adjust_algos[][3] = { 27 {}, /* NO_CHANGE */ 28 { NM, N, 1 }, /* N:1, N:1 */ 29 { 3, 2, 2 }, /* 3:2:2 */ 30 { 5, 2, 2 }, /* 5:2:2 */ 31 { N, 1, 1 }, /* N:1:1 */ 32 33 { N, 1 }, /* N:1 */ 34 35 { N, 1 }, /* N:1 */ 36 { 3, 2 }, 37 { 4, 3 }, 38 { 5, 4 }, 39 40 { N, 1 } 41 }; 42 43 static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2, 44 int m1, int m2, int round_flag) 45 { 46 unsigned long rem, div; 47 int the_one = 0; 48 49 pr_debug( "Actual values: r1 = %ld\n", r1); 50 pr_debug( "...............r2 = %ld\n", r2); 51 52 if (m1 == m2) { 53 r2 = r1; 54 pr_debug( "setting equal rates: r2 now %ld\n", r2); 55 } else if ((m2 == N && m1 == 1) || 56 (m2 == NM && m1 == N)) { /* N:1 or NM:N */ 57 pr_debug( "Setting rates as 1:N (N:N*M)\n"); 58 rem = r2 % r1; 59 pr_debug( "...remainder = %ld\n", rem); 60 if (rem) { 61 div = r2 / r1; 62 pr_debug( "...div = %ld\n", div); 63 switch (round_flag) { 64 case ROUND_NEAREST: 65 the_one = rem >= r1/2 ? 1 : 0; break; 66 case ROUND_UP: 67 the_one = 1; break; 68 case ROUND_DOWN: 69 the_one = 0; break; 70 } 71 72 r2 = r1 * (div + the_one); 73 pr_debug( "...setting r2 to %ld\n", r2); 74 } 75 } else if ((m2 == 1 && m1 == N) || 76 (m2 == N && m1 == NM)) { /* 1:N or N:NM */ 77 pr_debug( "Setting rates as N:1 (N*M:N)\n"); 78 rem = r1 % r2; 79 pr_debug( "...remainder = %ld\n", rem); 80 if (rem) { 81 div = r1 / r2; 82 pr_debug( "...div = %ld\n", div); 83 switch (round_flag) { 84 case ROUND_NEAREST: 85 the_one = rem > r2/2 ? 1 : 0; break; 86 case ROUND_UP: 87 the_one = 0; break; 88 case ROUND_DOWN: 89 the_one = 1; break; 90 } 91 92 r2 = r1 / (div + the_one); 93 pr_debug( "...setting r2 to %ld\n", r2); 94 } 95 } else { /* value:value */ 96 pr_debug( "Setting rates as %d:%d\n", m1, m2); 97 div = r1 / m1; 98 r2 = div * m2; 99 pr_debug( "...div = %ld\n", div); 100 pr_debug( "...setting r2 to %ld\n", r2); 101 } 102 103 return r2; 104 } 105 106 static void adjust_clocks(int originate, int *l, unsigned long v[], 107 int n_in_line) 108 { 109 int x; 110 111 pr_debug( "Go down from %d...\n", originate); 112 /* go up recalculation clocks */ 113 for (x = originate; x>0; x -- ) 114 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1], 115 l[x], l[x-1], 116 ROUND_UP); 117 118 pr_debug( "Go up from %d...\n", originate); 119 /* go down recalculation clocks */ 120 for (x = originate; x<n_in_line - 1; x ++ ) 121 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1], 122 l[x], l[x+1], 123 ROUND_UP); 124 } 125 126 127 /* 128 * SH7722 uses a common set of multipliers and divisors, so this 129 * is quite simple.. 130 */ 131 132 /* 133 * Instead of having two separate multipliers/divisors set, like this: 134 * 135 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 136 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 137 * 138 * I created the divisors2 array, which is used to calculate rate like 139 * rate = parent * 2 / divisors2[ divisor ]; 140 */ 141 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 142 143 static void master_clk_recalc(struct clk *clk) 144 { 145 unsigned frqcr = ctrl_inl(FRQCR); 146 147 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1); 148 } 149 150 static void master_clk_init(struct clk *clk) 151 { 152 clk->parent = NULL; 153 clk->flags |= CLK_RATE_PROPAGATES; 154 clk->rate = CONFIG_SH_PCLK_FREQ; 155 master_clk_recalc(clk); 156 } 157 158 159 static void module_clk_recalc(struct clk *clk) 160 { 161 unsigned long frqcr = ctrl_inl(FRQCR); 162 163 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1); 164 } 165 166 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id) 167 { 168 int div = rate / clk->rate; 169 int master_divs[] = { 2, 3, 4, 6, 8, 16 }; 170 int index; 171 unsigned long frqcr; 172 173 for (index = 1; index < ARRAY_SIZE(master_divs); index++) 174 if (div >= master_divs[index - 1] && div < master_divs[index]) 175 break; 176 177 if (index >= ARRAY_SIZE(master_divs)) 178 index = ARRAY_SIZE(master_divs); 179 div = master_divs[index - 1]; 180 181 frqcr = ctrl_inl(FRQCR); 182 frqcr &= ~(0xF << 24); 183 frqcr |= ( (div-1) << 24); 184 ctrl_outl(frqcr, FRQCR); 185 186 return 0; 187 } 188 189 static struct clk_ops sh7722_master_clk_ops = { 190 .init = master_clk_init, 191 .recalc = master_clk_recalc, 192 .set_rate = master_clk_setrate, 193 }; 194 195 static struct clk_ops sh7722_module_clk_ops = { 196 .recalc = module_clk_recalc, 197 }; 198 199 struct frqcr_context { 200 unsigned mask; 201 unsigned shift; 202 }; 203 204 struct frqcr_context sh7722_get_clk_context(const char *name) 205 { 206 struct frqcr_context ctx = { 0, }; 207 208 if (!strcmp(name, "peripheral_clk")) { 209 ctx.shift = 0; 210 ctx.mask = 0xF; 211 } else if (!strcmp(name, "sdram_clk")) { 212 ctx.shift = 4; 213 ctx.mask = 0xF; 214 } else if (!strcmp(name, "bus_clk")) { 215 ctx.shift = 8; 216 ctx.mask = 0xF; 217 } else if (!strcmp(name, "sh_clk")) { 218 ctx.shift = 12; 219 ctx.mask = 0xF; 220 } else if (!strcmp(name, "umem_clk")) { 221 ctx.shift = 16; 222 ctx.mask = 0xF; 223 } else if (!strcmp(name, "cpu_clk")) { 224 ctx.shift = 20; 225 ctx.mask = 7; 226 } 227 return ctx; 228 } 229 230 /** 231 * sh7722_find_divisors - find divisor for setting rate 232 * 233 * All sh7722 clocks use the same set of multipliers/divisors. This function 234 * chooses correct divisor to set the rate of clock with parent clock that 235 * generates frequency of 'parent_rate' 236 * 237 * @parent_rate: rate of parent clock 238 * @rate: requested rate to be set 239 */ 240 static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) 241 { 242 unsigned div2 = parent_rate * 2 / rate; 243 int index; 244 245 if (rate > parent_rate) 246 return -EINVAL; 247 248 for (index = 1; index < ARRAY_SIZE(divisors2); index++) { 249 if (div2 > divisors2[index] && div2 <= divisors2[index]) 250 break; 251 } 252 if (index >= ARRAY_SIZE(divisors2)) 253 index = ARRAY_SIZE(divisors2) - 1; 254 return divisors2[index]; 255 } 256 257 static void sh7722_frqcr_recalc(struct clk *clk) 258 { 259 struct frqcr_context ctx = sh7722_get_clk_context(clk->name); 260 unsigned long frqcr = ctrl_inl(FRQCR); 261 int index; 262 263 index = (frqcr >> ctx.shift) & ctx.mask; 264 clk->rate = clk->parent->rate * 2 / divisors2[index]; 265 } 266 267 static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, 268 int algo_id) 269 { 270 struct frqcr_context ctx = sh7722_get_clk_context(clk->name); 271 unsigned long parent_rate = clk->parent->rate; 272 int div; 273 unsigned long frqcr; 274 int err = 0; 275 276 /* pretty invalid */ 277 if (parent_rate < rate) 278 return -EINVAL; 279 280 /* look for multiplier/divisor pair */ 281 div = sh7722_find_divisors(parent_rate, rate); 282 if (div<0) 283 return div; 284 285 /* calculate new value of clock rate */ 286 clk->rate = parent_rate * 2 / div; 287 frqcr = ctrl_inl(FRQCR); 288 289 /* FIXME: adjust as algo_id specifies */ 290 if (algo_id != NO_CHANGE) { 291 int originator; 292 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" }; 293 char *algo_group_2[] = { "sh_clk", "bus_clk" }; 294 char *algo_group_3[] = { "sh_clk", "sdram_clk" }; 295 char *algo_group_4[] = { "bus_clk", "peripheral_clk" }; 296 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" }; 297 char **algo_current = NULL; 298 /* 3 is the maximum number of clocks in relation */ 299 struct clk *ck[3]; 300 unsigned long values[3]; /* the same comment as above */ 301 int part_length = -1; 302 int i; 303 304 /* 305 * all the steps below only required if adjustion was 306 * requested 307 */ 308 if (algo_id == IUS_N1_N1 || 309 algo_id == IUS_322 || 310 algo_id == IUS_522 || 311 algo_id == IUS_N11) { 312 algo_current = algo_group_1; 313 part_length = 3; 314 } 315 if (algo_id == SB_N1) { 316 algo_current = algo_group_2; 317 part_length = 2; 318 } 319 if (algo_id == SB3_N1 || 320 algo_id == SB3_32 || 321 algo_id == SB3_43 || 322 algo_id == SB3_54) { 323 algo_current = algo_group_3; 324 part_length = 2; 325 } 326 if (algo_id == BP_N1) { 327 algo_current = algo_group_4; 328 part_length = 2; 329 } 330 if (algo_id == IP_N1) { 331 algo_current = algo_group_5; 332 part_length = 2; 333 } 334 if (!algo_current) 335 goto incorrect_algo_id; 336 337 originator = -1; 338 for (i = 0; i < part_length; i ++ ) { 339 if (originator >= 0 && !strcmp(clk->name, 340 algo_current[i])) 341 originator = i; 342 ck[i] = clk_get(NULL, algo_current[i]); 343 values[i] = clk_get_rate(ck[i]); 344 } 345 346 if (originator >= 0) 347 adjust_clocks(originator, adjust_algos[algo_id], 348 values, part_length); 349 350 for (i = 0; i < part_length; i ++ ) { 351 struct frqcr_context part_ctx; 352 int part_div; 353 354 if (likely(!err)) { 355 part_div = sh7722_find_divisors(parent_rate, 356 rate); 357 if (part_div > 0) { 358 part_ctx = sh7722_get_clk_context( 359 ck[i]->name); 360 frqcr &= ~(part_ctx.mask << 361 part_ctx.shift); 362 frqcr |= part_div << part_ctx.shift; 363 } else 364 err = part_div; 365 } 366 367 ck[i]->ops->recalc(ck[i]); 368 clk_put(ck[i]); 369 } 370 } 371 372 /* was there any error during recalculation ? If so, bail out.. */ 373 if (unlikely(err!=0)) 374 goto out_err; 375 376 /* clear FRQCR bits */ 377 frqcr &= ~(ctx.mask << ctx.shift); 378 frqcr |= div << ctx.shift; 379 380 /* ...and perform actual change */ 381 ctrl_outl(frqcr, FRQCR); 382 return 0; 383 384 incorrect_algo_id: 385 return -EINVAL; 386 out_err: 387 return err; 388 } 389 390 static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate) 391 { 392 unsigned long parent_rate = clk->parent->rate; 393 int div; 394 395 /* look for multiplier/divisor pair */ 396 div = sh7722_find_divisors(parent_rate, rate); 397 if (div < 0) 398 return clk->rate; 399 400 /* calculate new value of clock rate */ 401 return parent_rate * 2 / div; 402 } 403 404 static struct clk_ops sh7722_frqcr_clk_ops = { 405 .recalc = sh7722_frqcr_recalc, 406 .set_rate = sh7722_frqcr_set_rate, 407 .round_rate = sh7722_frqcr_round_rate, 408 }; 409 410 /* 411 * clock ops methods for SIU A/B and IrDA clock 412 * 413 */ 414 static int sh7722_siu_which(struct clk *clk) 415 { 416 if (!strcmp(clk->name, "siu_a_clk")) 417 return 0; 418 if (!strcmp(clk->name, "siu_b_clk")) 419 return 1; 420 #if defined(CONFIG_CPU_SUBTYPE_SH7722) 421 if (!strcmp(clk->name, "irda_clk")) 422 return 2; 423 #endif 424 return -EINVAL; 425 } 426 427 static unsigned long sh7722_siu_regs[] = { 428 [0] = SCLKACR, 429 [1] = SCLKBCR, 430 #if defined(CONFIG_CPU_SUBTYPE_SH7722) 431 [2] = IrDACLKCR, 432 #endif 433 }; 434 435 static int sh7722_siu_start_stop(struct clk *clk, int enable) 436 { 437 int siu = sh7722_siu_which(clk); 438 unsigned long r; 439 440 if (siu < 0) 441 return siu; 442 BUG_ON(siu > 2); 443 r = ctrl_inl(sh7722_siu_regs[siu]); 444 if (enable) 445 ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]); 446 else 447 ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]); 448 return 0; 449 } 450 451 static void sh7722_siu_enable(struct clk *clk) 452 { 453 sh7722_siu_start_stop(clk, 1); 454 } 455 456 static void sh7722_siu_disable(struct clk *clk) 457 { 458 sh7722_siu_start_stop(clk, 0); 459 } 460 461 static void sh7722_video_enable(struct clk *clk) 462 { 463 unsigned long r; 464 465 r = ctrl_inl(VCLKCR); 466 ctrl_outl( r & ~(1<<8), VCLKCR); 467 } 468 469 static void sh7722_video_disable(struct clk *clk) 470 { 471 unsigned long r; 472 473 r = ctrl_inl(VCLKCR); 474 ctrl_outl( r | (1<<8), VCLKCR); 475 } 476 477 static int sh7722_video_set_rate(struct clk *clk, unsigned long rate, 478 int algo_id) 479 { 480 unsigned long r; 481 482 r = ctrl_inl(VCLKCR); 483 r &= ~0x3F; 484 r |= ((clk->parent->rate / rate - 1) & 0x3F); 485 ctrl_outl(r, VCLKCR); 486 return 0; 487 } 488 489 static void sh7722_video_recalc(struct clk *clk) 490 { 491 unsigned long r; 492 493 r = ctrl_inl(VCLKCR); 494 clk->rate = clk->parent->rate / ((r & 0x3F) + 1); 495 } 496 497 static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) 498 { 499 int siu = sh7722_siu_which(clk); 500 unsigned long r; 501 int div; 502 503 if (siu < 0) 504 return siu; 505 BUG_ON(siu > 2); 506 r = ctrl_inl(sh7722_siu_regs[siu]); 507 div = sh7722_find_divisors(clk->parent->rate, rate); 508 if (div < 0) 509 return div; 510 r = (r & ~0xF) | div; 511 ctrl_outl(r, sh7722_siu_regs[siu]); 512 return 0; 513 } 514 515 static void sh7722_siu_recalc(struct clk *clk) 516 { 517 int siu = sh7722_siu_which(clk); 518 unsigned long r; 519 520 if (siu < 0) 521 return /* siu */ ; 522 BUG_ON(siu > 2); 523 r = ctrl_inl(sh7722_siu_regs[siu]); 524 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF]; 525 } 526 527 static struct clk_ops sh7722_siu_clk_ops = { 528 .recalc = sh7722_siu_recalc, 529 .set_rate = sh7722_siu_set_rate, 530 .enable = sh7722_siu_enable, 531 .disable = sh7722_siu_disable, 532 }; 533 534 static struct clk_ops sh7722_video_clk_ops = { 535 .recalc = sh7722_video_recalc, 536 .set_rate = sh7722_video_set_rate, 537 .enable = sh7722_video_enable, 538 .disable = sh7722_video_disable, 539 }; 540 /* 541 * and at last, clock definitions themselves 542 */ 543 static struct clk sh7722_umem_clock = { 544 .name = "umem_clk", 545 .ops = &sh7722_frqcr_clk_ops, 546 }; 547 548 static struct clk sh7722_sh_clock = { 549 .name = "sh_clk", 550 .ops = &sh7722_frqcr_clk_ops, 551 }; 552 553 static struct clk sh7722_peripheral_clock = { 554 .name = "peripheral_clk", 555 .ops = &sh7722_frqcr_clk_ops, 556 }; 557 558 static struct clk sh7722_sdram_clock = { 559 .name = "sdram_clk", 560 .ops = &sh7722_frqcr_clk_ops, 561 }; 562 563 /* 564 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops 565 * methods of clk_ops determine which register they should access by 566 * examining clk->name field 567 */ 568 static struct clk sh7722_siu_a_clock = { 569 .name = "siu_a_clk", 570 .ops = &sh7722_siu_clk_ops, 571 }; 572 573 static struct clk sh7722_siu_b_clock = { 574 .name = "siu_b_clk", 575 .ops = &sh7722_siu_clk_ops, 576 }; 577 578 #if defined(CONFIG_CPU_SUBTYPE_SH7722) 579 static struct clk sh7722_irda_clock = { 580 .name = "irda_clk", 581 .ops = &sh7722_siu_clk_ops, 582 }; 583 #endif 584 585 static struct clk sh7722_video_clock = { 586 .name = "video_clk", 587 .ops = &sh7722_video_clk_ops, 588 }; 589 590 static struct clk *sh7722_clocks[] = { 591 &sh7722_umem_clock, 592 &sh7722_sh_clock, 593 &sh7722_peripheral_clock, 594 &sh7722_sdram_clock, 595 &sh7722_siu_a_clock, 596 &sh7722_siu_b_clock, 597 #if defined(CONFIG_CPU_SUBTYPE_SH7722) 598 &sh7722_irda_clock, 599 #endif 600 &sh7722_video_clock, 601 }; 602 603 /* 604 * init in order: master, module, bus, cpu 605 */ 606 struct clk_ops *onchip_ops[] = { 607 &sh7722_master_clk_ops, 608 &sh7722_module_clk_ops, 609 &sh7722_frqcr_clk_ops, 610 &sh7722_frqcr_clk_ops, 611 }; 612 613 void __init 614 arch_init_clk_ops(struct clk_ops **ops, int type) 615 { 616 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops)); 617 *ops = onchip_ops[type]; 618 } 619 620 int __init arch_clk_init(void) 621 { 622 struct clk *master; 623 int i; 624 625 master = clk_get(NULL, "master_clk"); 626 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { 627 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); 628 sh7722_clocks[i]->parent = master; 629 clk_register(sh7722_clocks[i]); 630 } 631 clk_put(master); 632 return 0; 633 } 634