1 /*
2  * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
3  *
4  * SH7366 clock framework support
5  *
6  * Copyright (C) 2009 Magnus Damm
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clkdev.h>
25 #include <asm/clock.h>
26 
27 /* SH7366 registers */
28 #define FRQCR		0xa4150000
29 #define VCLKCR		0xa4150004
30 #define SCLKACR		0xa4150008
31 #define SCLKBCR		0xa415000c
32 #define PLLCR		0xa4150024
33 #define MSTPCR0		0xa4150030
34 #define MSTPCR1		0xa4150034
35 #define MSTPCR2		0xa4150038
36 #define DLLFRQ		0xa4150050
37 
38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
39 static struct clk r_clk = {
40 	.rate           = 32768,
41 };
42 
43 /*
44  * Default rate for the root input clock, reset this with clk_set_rate()
45  * from the platform code.
46  */
47 struct clk extal_clk = {
48 	.rate		= 33333333,
49 };
50 
51 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
52 static unsigned long dll_recalc(struct clk *clk)
53 {
54 	unsigned long mult;
55 
56 	if (__raw_readl(PLLCR) & 0x1000)
57 		mult = __raw_readl(DLLFRQ);
58 	else
59 		mult = 0;
60 
61 	return clk->parent->rate * mult;
62 }
63 
64 static struct sh_clk_ops dll_clk_ops = {
65 	.recalc		= dll_recalc,
66 };
67 
68 static struct clk dll_clk = {
69 	.ops		= &dll_clk_ops,
70 	.parent		= &r_clk,
71 	.flags		= CLK_ENABLE_ON_INIT,
72 };
73 
74 static unsigned long pll_recalc(struct clk *clk)
75 {
76 	unsigned long mult = 1;
77 	unsigned long div = 1;
78 
79 	if (__raw_readl(PLLCR) & 0x4000)
80 		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
81 	else
82 		div = 2;
83 
84 	return (clk->parent->rate * mult) / div;
85 }
86 
87 static struct sh_clk_ops pll_clk_ops = {
88 	.recalc		= pll_recalc,
89 };
90 
91 static struct clk pll_clk = {
92 	.ops		= &pll_clk_ops,
93 	.flags		= CLK_ENABLE_ON_INIT,
94 };
95 
96 struct clk *main_clks[] = {
97 	&r_clk,
98 	&extal_clk,
99 	&dll_clk,
100 	&pll_clk,
101 };
102 
103 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
104 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
105 
106 static struct clk_div_mult_table div4_div_mult_table = {
107 	.divisors = divisors,
108 	.nr_divisors = ARRAY_SIZE(divisors),
109 	.multipliers = multipliers,
110 	.nr_multipliers = ARRAY_SIZE(multipliers),
111 };
112 
113 static struct clk_div4_table div4_table = {
114 	.div_mult_table = &div4_div_mult_table,
115 };
116 
117 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
118        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
119 
120 #define DIV4(_reg, _bit, _mask, _flags) \
121   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
122 
123 struct clk div4_clks[DIV4_NR] = {
124 	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
130 	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
131 	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
132 };
133 
134 enum { DIV6_V, DIV6_NR };
135 
136 struct clk div6_clks[DIV6_NR] = {
137 	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
138 };
139 
140 #define MSTP(_parent, _reg, _bit, _flags) \
141   SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
142 
143 enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
144        MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
145        MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
146        MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
147        MSTP109, MSTP100,
148        MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
149        MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
150        MSTP_NR };
151 
152 static struct clk mstp_clks[MSTP_NR] = {
153 	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
154 	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
157 	[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
158 	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
159 	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
160 	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
161 	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
162 	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
163 	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
164 	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
165 	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
166 	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
167 	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
168 	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
169 	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
170 	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
171 	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
172 	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
173 	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
174 	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
175 
176 	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
177 
178 	[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
179 	[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
180 	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
181 	[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
182 	[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
183 	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
184 	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
185 	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
186 	[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
187 	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
188 	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
189 	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
190 	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
191 	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
192 	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
193 };
194 
195 static struct clk_lookup lookups[] = {
196 	/* main clocks */
197 	CLKDEV_CON_ID("rclk", &r_clk),
198 	CLKDEV_CON_ID("extal", &extal_clk),
199 	CLKDEV_CON_ID("dll_clk", &dll_clk),
200 	CLKDEV_CON_ID("pll_clk", &pll_clk),
201 
202 	/* DIV4 clocks */
203 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
204 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
205 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
206 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
207 	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
208 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
209 	CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
210 	CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
211 
212 	/* DIV6 clocks */
213 	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
214 
215 	/* MSTP32 clocks */
216 	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
217 	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
218 	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
219 	CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
220 	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
221 	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
222 	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
223 	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
224 	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
225 	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
226 	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
227 	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
228 	CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
229 	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
230 	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
231 	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
232 
233 	CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]),
234 	CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]),
235 	CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]),
236 
237 	CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
238 	CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
239 	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
240 	CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
241 	CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
242 	CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
243 	CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
244 	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
245 	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
246 	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
247 	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
248 	CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
249 	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
250 	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
251 	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
252 	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
253 	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
254 	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
255 };
256 
257 int __init arch_clk_init(void)
258 {
259 	int k, ret = 0;
260 
261 	/* autodetect extal or dll configuration */
262 	if (__raw_readl(PLLCR) & 0x1000)
263 		pll_clk.parent = &dll_clk;
264 	else
265 		pll_clk.parent = &extal_clk;
266 
267 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
268 		ret = clk_register(main_clks[k]);
269 
270 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
271 
272 	if (!ret)
273 		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
274 
275 	if (!ret)
276 		ret = sh_clk_div6_register(div6_clks, DIV6_NR);
277 
278 	if (!ret)
279 		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
280 
281 	return ret;
282 }
283