1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c 3 * 4 * SH7343 clock framework support 5 * 6 * Copyright (C) 2009 Magnus Damm 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <asm/clkdev.h> 25 #include <asm/clock.h> 26 27 /* SH7343 registers */ 28 #define FRQCR 0xa4150000 29 #define VCLKCR 0xa4150004 30 #define SCLKACR 0xa4150008 31 #define SCLKBCR 0xa415000c 32 #define PLLCR 0xa4150024 33 #define MSTPCR0 0xa4150030 34 #define MSTPCR1 0xa4150034 35 #define MSTPCR2 0xa4150038 36 #define DLLFRQ 0xa4150050 37 38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 39 static struct clk r_clk = { 40 .name = "rclk", 41 .id = -1, 42 .rate = 32768, 43 }; 44 45 /* 46 * Default rate for the root input clock, reset this with clk_set_rate() 47 * from the platform code. 48 */ 49 struct clk extal_clk = { 50 .name = "extal", 51 .id = -1, 52 .rate = 33333333, 53 }; 54 55 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */ 56 static unsigned long dll_recalc(struct clk *clk) 57 { 58 unsigned long mult; 59 60 if (__raw_readl(PLLCR) & 0x1000) 61 mult = __raw_readl(DLLFRQ); 62 else 63 mult = 0; 64 65 return clk->parent->rate * mult; 66 } 67 68 static struct clk_ops dll_clk_ops = { 69 .recalc = dll_recalc, 70 }; 71 72 static struct clk dll_clk = { 73 .name = "dll_clk", 74 .id = -1, 75 .ops = &dll_clk_ops, 76 .parent = &r_clk, 77 .flags = CLK_ENABLE_ON_INIT, 78 }; 79 80 static unsigned long pll_recalc(struct clk *clk) 81 { 82 unsigned long mult = 1; 83 84 if (__raw_readl(PLLCR) & 0x4000) 85 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); 86 87 return clk->parent->rate * mult; 88 } 89 90 static struct clk_ops pll_clk_ops = { 91 .recalc = pll_recalc, 92 }; 93 94 static struct clk pll_clk = { 95 .name = "pll_clk", 96 .id = -1, 97 .ops = &pll_clk_ops, 98 .flags = CLK_ENABLE_ON_INIT, 99 }; 100 101 struct clk *main_clks[] = { 102 &r_clk, 103 &extal_clk, 104 &dll_clk, 105 &pll_clk, 106 }; 107 108 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 109 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 110 111 static struct clk_div_mult_table div4_div_mult_table = { 112 .divisors = divisors, 113 .nr_divisors = ARRAY_SIZE(divisors), 114 .multipliers = multipliers, 115 .nr_multipliers = ARRAY_SIZE(multipliers), 116 }; 117 118 static struct clk_div4_table div4_table = { 119 .div_mult_table = &div4_div_mult_table, 120 }; 121 122 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 123 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 124 125 #define DIV4(_str, _reg, _bit, _mask, _flags) \ 126 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 127 128 struct clk div4_clks[DIV4_NR] = { 129 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 130 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 131 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 132 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 133 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 134 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 135 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 136 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 137 }; 138 139 enum { DIV6_V, DIV6_NR }; 140 141 struct clk div6_clks[DIV6_NR] = { 142 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 143 }; 144 145 #define MSTP(_parent, _reg, _bit, _flags) \ 146 SH_CLK_MSTP32(_parent, _reg, _bit, _flags) 147 148 enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, 149 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, 150 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010, 151 MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001, 152 MSTP109, MSTP108, MSTP100, 153 MSTP225, MSTP224, MSTP218, MSTP217, MSTP216, 154 MSTP214, MSTP213, MSTP212, MSTP211, MSTP208, 155 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 156 MSTP_NR }; 157 158 static struct clk mstp_clks[MSTP_NR] = { 159 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 160 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 161 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 162 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 163 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 164 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), 165 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), 166 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), 167 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), 168 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), 169 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), 170 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), 171 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), 172 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), 173 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), 174 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), 175 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), 176 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), 177 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), 178 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), 179 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), 180 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), 181 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), 182 183 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 184 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0), 185 186 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), 187 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), 188 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), 189 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), 190 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), 191 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), 192 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), 193 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), 194 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), 195 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 196 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 197 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 198 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 199 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 200 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 201 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 202 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), 203 }; 204 205 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 206 207 static struct clk_lookup lookups[] = { 208 /* DIV4 clocks */ 209 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 210 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 211 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 212 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 213 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), 214 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 215 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), 216 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), 217 218 /* DIV6 clocks */ 219 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 220 221 /* MSTP32 clocks */ 222 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]), 223 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]), 224 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]), 225 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]), 226 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), 227 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), 228 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), 229 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), 230 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), 231 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), 232 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]), 233 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]), 234 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]), 235 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), 236 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), 237 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), 238 { 239 /* SCIF0 */ 240 .dev_id = "sh-sci.0", 241 .con_id = "sci_fck", 242 .clk = &mstp_clks[MSTP007], 243 }, { 244 /* SCIF1 */ 245 .dev_id = "sh-sci.1", 246 .con_id = "sci_fck", 247 .clk = &mstp_clks[MSTP006], 248 }, { 249 /* SCIF2 */ 250 .dev_id = "sh-sci.2", 251 .con_id = "sci_fck", 252 .clk = &mstp_clks[MSTP005], 253 }, { 254 /* SCIF3 */ 255 .dev_id = "sh-sci.3", 256 .con_id = "sci_fck", 257 .clk = &mstp_clks[MSTP004], 258 }, 259 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]), 260 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]), 261 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]), 262 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]), 263 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]), 264 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]), 265 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]), 266 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), 267 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]), 268 CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]), 269 CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]), 270 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]), 271 CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]), 272 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]), 273 CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]), 274 CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]), 275 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]), 276 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]), 277 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]), 278 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]), 279 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]), 280 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]), 281 }; 282 283 int __init arch_clk_init(void) 284 { 285 int k, ret = 0; 286 287 /* autodetect extal or dll configuration */ 288 if (__raw_readl(PLLCR) & 0x1000) 289 pll_clk.parent = &dll_clk; 290 else 291 pll_clk.parent = &extal_clk; 292 293 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 294 ret = clk_register(main_clks[k]); 295 296 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 297 298 if (!ret) 299 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 300 301 if (!ret) 302 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 303 304 if (!ret) 305 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 306 307 return ret; 308 } 309