1 /* 2 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c 3 * 4 * SH7343 clock framework support 5 * 6 * Copyright (C) 2009 Magnus Damm 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <asm/clock.h> 25 26 /* SH7343 registers */ 27 #define FRQCR 0xa4150000 28 #define VCLKCR 0xa4150004 29 #define SCLKACR 0xa4150008 30 #define SCLKBCR 0xa415000c 31 #define PLLCR 0xa4150024 32 #define MSTPCR0 0xa4150030 33 #define MSTPCR1 0xa4150034 34 #define MSTPCR2 0xa4150038 35 #define DLLFRQ 0xa4150050 36 37 /* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38 static struct clk r_clk = { 39 .name = "rclk", 40 .id = -1, 41 .rate = 32768, 42 }; 43 44 /* 45 * Default rate for the root input clock, reset this with clk_set_rate() 46 * from the platform code. 47 */ 48 struct clk extal_clk = { 49 .name = "extal", 50 .id = -1, 51 .rate = 33333333, 52 }; 53 54 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */ 55 static unsigned long dll_recalc(struct clk *clk) 56 { 57 unsigned long mult; 58 59 if (__raw_readl(PLLCR) & 0x1000) 60 mult = __raw_readl(DLLFRQ); 61 else 62 mult = 0; 63 64 return clk->parent->rate * mult; 65 } 66 67 static struct clk_ops dll_clk_ops = { 68 .recalc = dll_recalc, 69 }; 70 71 static struct clk dll_clk = { 72 .name = "dll_clk", 73 .id = -1, 74 .ops = &dll_clk_ops, 75 .parent = &r_clk, 76 .flags = CLK_ENABLE_ON_INIT, 77 }; 78 79 static unsigned long pll_recalc(struct clk *clk) 80 { 81 unsigned long mult = 1; 82 83 if (__raw_readl(PLLCR) & 0x4000) 84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); 85 86 return clk->parent->rate * mult; 87 } 88 89 static struct clk_ops pll_clk_ops = { 90 .recalc = pll_recalc, 91 }; 92 93 static struct clk pll_clk = { 94 .name = "pll_clk", 95 .id = -1, 96 .ops = &pll_clk_ops, 97 .flags = CLK_ENABLE_ON_INIT, 98 }; 99 100 struct clk *main_clks[] = { 101 &r_clk, 102 &extal_clk, 103 &dll_clk, 104 &pll_clk, 105 }; 106 107 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 108 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 109 110 static struct clk_div_mult_table div4_div_mult_table = { 111 .divisors = divisors, 112 .nr_divisors = ARRAY_SIZE(divisors), 113 .multipliers = multipliers, 114 .nr_multipliers = ARRAY_SIZE(multipliers), 115 }; 116 117 static struct clk_div4_table div4_table = { 118 .div_mult_table = &div4_div_mult_table, 119 }; 120 121 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 122 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 123 124 #define DIV4(_str, _reg, _bit, _mask, _flags) \ 125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 126 127 struct clk div4_clks[DIV4_NR] = { 128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 136 }; 137 138 struct clk div6_clks[] = { 139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 140 }; 141 142 #define MSTP(_str, _parent, _reg, _bit, _flags) \ 143 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 144 145 static struct clk mstp_clks[] = { 146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 149 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 165 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), 166 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 167 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 168 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 169 170 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 171 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 172 173 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 174 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 177 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 178 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 179 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 180 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 181 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 182 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 183 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 184 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 185 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 186 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 187 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 188 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 189 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 190 }; 191 192 int __init arch_clk_init(void) 193 { 194 int k, ret = 0; 195 196 /* autodetect extal or dll configuration */ 197 if (__raw_readl(PLLCR) & 0x1000) 198 pll_clk.parent = &dll_clk; 199 else 200 pll_clk.parent = &extal_clk; 201 202 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 203 ret = clk_register(main_clks[k]); 204 205 if (!ret) 206 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 207 208 if (!ret) 209 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 210 211 if (!ret) 212 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 213 214 return ret; 215 } 216