1 /* 2 * SH7760 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/sh_timer.h> 14 #include <linux/sh_intc.h> 15 #include <linux/serial_sci.h> 16 #include <linux/io.h> 17 18 enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRL0, IRL1, IRL2, IRL3, 23 HUDI, GPIOI, DMAC, 24 IRQ4, IRQ5, IRQ6, IRQ7, 25 HCAN20, HCAN21, 26 SSI0, SSI1, 27 HAC0, HAC1, 28 I2C0, I2C1, 29 USB, LCDC, 30 DMABRG0, DMABRG1, DMABRG2, 31 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 32 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 33 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 34 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 35 HSPI, 36 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 37 MFI, ADC, CMT, 38 TMU0, TMU1, TMU2, 39 WDT, REF, 40 41 /* interrupt groups */ 42 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, 43 }; 44 45 static struct intc_vect vectors[] __initdata = { 46 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 47 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 48 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 49 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 50 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 51 INTC_VECT(DMAC, 0x6c0), 52 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 53 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 54 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 55 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960), 56 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0), 57 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0), 58 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20), 59 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0), 60 INTC_VECT(DMABRG2, 0xac0), 61 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 62 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 63 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20), 64 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60), 65 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0), 66 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0), 67 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20), 68 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60), 69 INTC_VECT(HSPI, 0xc80), 70 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20), 71 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60), 72 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 73 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 74 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 75 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 76 INTC_VECT(WDT, 0x560), 77 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 78 }; 79 80 static struct intc_group groups[] __initdata = { 81 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 82 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 83 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 84 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 85 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 86 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 87 }; 88 89 static struct intc_mask_reg mask_registers[] __initdata = { 90 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 91 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, 92 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, 93 0, DMABRG0, DMABRG1, DMABRG2, 94 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 95 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 96 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } }, 97 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */ 98 { 0, 0, 0, 0, 0, 0, 0, 0, 99 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 100 HSPI, MMCIF0, MMCIF1, MMCIF2, 101 MMCIF3, 0, 0, 0, 0, 0, 0, 0, 102 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, 103 }; 104 105 static struct intc_prio_reg prio_registers[] __initdata = { 106 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 107 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 108 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, 109 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 110 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 111 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, 112 HAC0, HAC1, I2C0, I2C1 } }, 113 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, 114 SCIF1, SCIF2, SIM, HSPI } }, 115 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, 116 MFI, 0, ADC, CMT } }, 117 }; 118 119 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, 120 mask_registers, prio_registers, NULL); 121 122 static struct intc_vect vectors_irq[] __initdata = { 123 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 124 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 125 }; 126 127 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, 128 mask_registers, prio_registers, NULL); 129 130 static struct plat_sci_port scif0_platform_data = { 131 .flags = UPF_BOOT_AUTOCONF, 132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 133 .type = PORT_SCIF, 134 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 135 }; 136 137 static struct resource scif0_resources[] = { 138 DEFINE_RES_MEM(0xfe600000, 0x100), 139 DEFINE_RES_IRQ(evt2irq(0x880)), 140 DEFINE_RES_IRQ(evt2irq(0x8a0)), 141 DEFINE_RES_IRQ(evt2irq(0x8e0)), 142 DEFINE_RES_IRQ(evt2irq(0x8c0)), 143 }; 144 145 static struct platform_device scif0_device = { 146 .name = "sh-sci", 147 .id = 0, 148 .resource = scif0_resources, 149 .num_resources = ARRAY_SIZE(scif0_resources), 150 .dev = { 151 .platform_data = &scif0_platform_data, 152 }, 153 }; 154 155 static struct plat_sci_port scif1_platform_data = { 156 .flags = UPF_BOOT_AUTOCONF, 157 .type = PORT_SCIF, 158 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 160 }; 161 162 static struct resource scif1_resources[] = { 163 DEFINE_RES_MEM(0xfe610000, 0x100), 164 DEFINE_RES_IRQ(evt2irq(0xb00)), 165 DEFINE_RES_IRQ(evt2irq(0xb20)), 166 DEFINE_RES_IRQ(evt2irq(0xb60)), 167 DEFINE_RES_IRQ(evt2irq(0xb40)), 168 }; 169 170 static struct platform_device scif1_device = { 171 .name = "sh-sci", 172 .id = 1, 173 .resource = scif1_resources, 174 .num_resources = ARRAY_SIZE(scif1_resources), 175 .dev = { 176 .platform_data = &scif1_platform_data, 177 }, 178 }; 179 180 static struct plat_sci_port scif2_platform_data = { 181 .flags = UPF_BOOT_AUTOCONF, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .type = PORT_SCIF, 184 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 185 }; 186 187 static struct resource scif2_resources[] = { 188 DEFINE_RES_MEM(0xfe620000, 0x100), 189 DEFINE_RES_IRQ(evt2irq(0xb80)), 190 DEFINE_RES_IRQ(evt2irq(0xba0)), 191 DEFINE_RES_IRQ(evt2irq(0xbe0)), 192 DEFINE_RES_IRQ(evt2irq(0xbc0)), 193 }; 194 195 static struct platform_device scif2_device = { 196 .name = "sh-sci", 197 .id = 2, 198 .resource = scif2_resources, 199 .num_resources = ARRAY_SIZE(scif2_resources), 200 .dev = { 201 .platform_data = &scif2_platform_data, 202 }, 203 }; 204 205 static struct plat_sci_port scif3_platform_data = { 206 .flags = UPF_BOOT_AUTOCONF, 207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 208 .type = PORT_SCI, 209 .regshift = 2, 210 }; 211 212 static struct resource scif3_resources[] = { 213 DEFINE_RES_MEM(0xfe480000, 0x100), 214 DEFINE_RES_IRQ(evt2irq(0xc00)), 215 DEFINE_RES_IRQ(evt2irq(0xc20)), 216 DEFINE_RES_IRQ(evt2irq(0xc40)), 217 }; 218 219 static struct platform_device scif3_device = { 220 .name = "sh-sci", 221 .id = 3, 222 .resource = scif3_resources, 223 .num_resources = ARRAY_SIZE(scif3_resources), 224 .dev = { 225 .platform_data = &scif3_platform_data, 226 }, 227 }; 228 229 static struct sh_timer_config tmu0_platform_data = { 230 .channels_mask = 7, 231 }; 232 233 static struct resource tmu0_resources[] = { 234 DEFINE_RES_MEM(0xffd80000, 0x30), 235 DEFINE_RES_IRQ(evt2irq(0x400)), 236 DEFINE_RES_IRQ(evt2irq(0x420)), 237 DEFINE_RES_IRQ(evt2irq(0x440)), 238 }; 239 240 static struct platform_device tmu0_device = { 241 .name = "sh-tmu", 242 .id = 0, 243 .dev = { 244 .platform_data = &tmu0_platform_data, 245 }, 246 .resource = tmu0_resources, 247 .num_resources = ARRAY_SIZE(tmu0_resources), 248 }; 249 250 251 static struct platform_device *sh7760_devices[] __initdata = { 252 &scif0_device, 253 &scif1_device, 254 &scif2_device, 255 &scif3_device, 256 &tmu0_device, 257 }; 258 259 static int __init sh7760_devices_setup(void) 260 { 261 return platform_add_devices(sh7760_devices, 262 ARRAY_SIZE(sh7760_devices)); 263 } 264 arch_initcall(sh7760_devices_setup); 265 266 static struct platform_device *sh7760_early_devices[] __initdata = { 267 &scif0_device, 268 &scif1_device, 269 &scif2_device, 270 &scif3_device, 271 &tmu0_device, 272 }; 273 274 void __init plat_early_device_setup(void) 275 { 276 early_platform_add_devices(sh7760_early_devices, 277 ARRAY_SIZE(sh7760_early_devices)); 278 } 279 280 #define INTC_ICR 0xffd00000UL 281 #define INTC_ICR_IRLM (1 << 7) 282 283 void __init plat_irq_setup_pins(int mode) 284 { 285 switch (mode) { 286 case IRQ_MODE_IRQ: 287 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 288 register_intc_controller(&intc_desc_irq); 289 break; 290 default: 291 BUG(); 292 } 293 } 294 295 void __init plat_irq_setup(void) 296 { 297 register_intc_controller(&intc_desc); 298 } 299