1 /* 2 * SH7760 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/sh_timer.h> 14 #include <linux/serial_sci.h> 15 #include <linux/io.h> 16 17 enum { 18 UNUSED = 0, 19 20 /* interrupt sources */ 21 IRL0, IRL1, IRL2, IRL3, 22 HUDI, GPIOI, DMAC, 23 IRQ4, IRQ5, IRQ6, IRQ7, 24 HCAN20, HCAN21, 25 SSI0, SSI1, 26 HAC0, HAC1, 27 I2C0, I2C1, 28 USB, LCDC, 29 DMABRG0, DMABRG1, DMABRG2, 30 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 31 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 32 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 33 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 34 HSPI, 35 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 36 MFI, ADC, CMT, 37 TMU0, TMU1, TMU2, 38 WDT, REF, 39 40 /* interrupt groups */ 41 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, 42 }; 43 44 static struct intc_vect vectors[] __initdata = { 45 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 46 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 47 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 48 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 49 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 50 INTC_VECT(DMAC, 0x6c0), 51 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 52 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 53 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 54 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960), 55 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0), 56 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0), 57 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20), 58 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0), 59 INTC_VECT(DMABRG2, 0xac0), 60 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 61 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 62 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20), 63 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60), 64 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0), 65 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0), 66 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20), 67 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60), 68 INTC_VECT(HSPI, 0xc80), 69 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20), 70 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60), 71 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 72 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 73 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 74 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 75 INTC_VECT(WDT, 0x560), 76 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 77 }; 78 79 static struct intc_group groups[] __initdata = { 80 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 81 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 82 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 83 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 84 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 85 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 86 }; 87 88 static struct intc_mask_reg mask_registers[] __initdata = { 89 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 90 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, 91 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, 92 0, DMABRG0, DMABRG1, DMABRG2, 93 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 94 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 95 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } }, 96 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */ 97 { 0, 0, 0, 0, 0, 0, 0, 0, 98 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 99 HSPI, MMCIF0, MMCIF1, MMCIF2, 100 MMCIF3, 0, 0, 0, 0, 0, 0, 0, 101 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, 102 }; 103 104 static struct intc_prio_reg prio_registers[] __initdata = { 105 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 106 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 107 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, 108 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 109 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 110 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, 111 HAC0, HAC1, I2C0, I2C1 } }, 112 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, 113 SCIF1, SCIF2, SIM, HSPI } }, 114 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, 115 MFI, 0, ADC, CMT } }, 116 }; 117 118 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, 119 mask_registers, prio_registers, NULL); 120 121 static struct intc_vect vectors_irq[] __initdata = { 122 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 123 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 124 }; 125 126 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, 127 mask_registers, prio_registers, NULL); 128 129 static struct plat_sci_port scif0_platform_data = { 130 .mapbase = 0xfe600000, 131 .flags = UPF_BOOT_AUTOCONF, 132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 133 .scbrr_algo_id = SCBRR_ALGO_2, 134 .type = PORT_SCIF, 135 .irqs = { 52, 53, 55, 54 }, 136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 137 }; 138 139 static struct platform_device scif0_device = { 140 .name = "sh-sci", 141 .id = 0, 142 .dev = { 143 .platform_data = &scif0_platform_data, 144 }, 145 }; 146 147 static struct plat_sci_port scif1_platform_data = { 148 .mapbase = 0xfe610000, 149 .flags = UPF_BOOT_AUTOCONF, 150 .type = PORT_SCIF, 151 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 152 .scbrr_algo_id = SCBRR_ALGO_2, 153 .irqs = { 72, 73, 75, 74 }, 154 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 155 }; 156 157 static struct platform_device scif1_device = { 158 .name = "sh-sci", 159 .id = 1, 160 .dev = { 161 .platform_data = &scif1_platform_data, 162 }, 163 }; 164 165 static struct plat_sci_port scif2_platform_data = { 166 .mapbase = 0xfe620000, 167 .flags = UPF_BOOT_AUTOCONF, 168 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 169 .scbrr_algo_id = SCBRR_ALGO_2, 170 .type = PORT_SCIF, 171 .irqs = { 76, 77, 79, 78 }, 172 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 173 }; 174 175 static struct platform_device scif2_device = { 176 .name = "sh-sci", 177 .id = 2, 178 .dev = { 179 .platform_data = &scif2_platform_data, 180 }, 181 }; 182 183 static struct plat_sci_port scif3_platform_data = { 184 .mapbase = 0xfe480000, 185 .flags = UPF_BOOT_AUTOCONF, 186 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 187 .scbrr_algo_id = SCBRR_ALGO_2, 188 .type = PORT_SCI, 189 .irqs = { 80, 81, 82, 0 }, 190 .regshift = 2, 191 }; 192 193 static struct platform_device scif3_device = { 194 .name = "sh-sci", 195 .id = 3, 196 .dev = { 197 .platform_data = &scif3_platform_data, 198 }, 199 }; 200 201 static struct sh_timer_config tmu0_platform_data = { 202 .channel_offset = 0x04, 203 .timer_bit = 0, 204 .clockevent_rating = 200, 205 }; 206 207 static struct resource tmu0_resources[] = { 208 [0] = { 209 .start = 0xffd80008, 210 .end = 0xffd80013, 211 .flags = IORESOURCE_MEM, 212 }, 213 [1] = { 214 .start = 16, 215 .flags = IORESOURCE_IRQ, 216 }, 217 }; 218 219 static struct platform_device tmu0_device = { 220 .name = "sh_tmu", 221 .id = 0, 222 .dev = { 223 .platform_data = &tmu0_platform_data, 224 }, 225 .resource = tmu0_resources, 226 .num_resources = ARRAY_SIZE(tmu0_resources), 227 }; 228 229 static struct sh_timer_config tmu1_platform_data = { 230 .channel_offset = 0x10, 231 .timer_bit = 1, 232 .clocksource_rating = 200, 233 }; 234 235 static struct resource tmu1_resources[] = { 236 [0] = { 237 .start = 0xffd80014, 238 .end = 0xffd8001f, 239 .flags = IORESOURCE_MEM, 240 }, 241 [1] = { 242 .start = 17, 243 .flags = IORESOURCE_IRQ, 244 }, 245 }; 246 247 static struct platform_device tmu1_device = { 248 .name = "sh_tmu", 249 .id = 1, 250 .dev = { 251 .platform_data = &tmu1_platform_data, 252 }, 253 .resource = tmu1_resources, 254 .num_resources = ARRAY_SIZE(tmu1_resources), 255 }; 256 257 static struct sh_timer_config tmu2_platform_data = { 258 .channel_offset = 0x1c, 259 .timer_bit = 2, 260 }; 261 262 static struct resource tmu2_resources[] = { 263 [0] = { 264 .start = 0xffd80020, 265 .end = 0xffd8002f, 266 .flags = IORESOURCE_MEM, 267 }, 268 [1] = { 269 .start = 18, 270 .flags = IORESOURCE_IRQ, 271 }, 272 }; 273 274 static struct platform_device tmu2_device = { 275 .name = "sh_tmu", 276 .id = 2, 277 .dev = { 278 .platform_data = &tmu2_platform_data, 279 }, 280 .resource = tmu2_resources, 281 .num_resources = ARRAY_SIZE(tmu2_resources), 282 }; 283 284 285 static struct platform_device *sh7760_devices[] __initdata = { 286 &scif0_device, 287 &scif1_device, 288 &scif2_device, 289 &scif3_device, 290 &tmu0_device, 291 &tmu1_device, 292 &tmu2_device, 293 }; 294 295 static int __init sh7760_devices_setup(void) 296 { 297 return platform_add_devices(sh7760_devices, 298 ARRAY_SIZE(sh7760_devices)); 299 } 300 arch_initcall(sh7760_devices_setup); 301 302 static struct platform_device *sh7760_early_devices[] __initdata = { 303 &scif0_device, 304 &scif1_device, 305 &scif2_device, 306 &scif3_device, 307 &tmu0_device, 308 &tmu1_device, 309 &tmu2_device, 310 }; 311 312 void __init plat_early_device_setup(void) 313 { 314 early_platform_add_devices(sh7760_early_devices, 315 ARRAY_SIZE(sh7760_early_devices)); 316 } 317 318 #define INTC_ICR 0xffd00000UL 319 #define INTC_ICR_IRLM (1 << 7) 320 321 void __init plat_irq_setup_pins(int mode) 322 { 323 switch (mode) { 324 case IRQ_MODE_IRQ: 325 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 326 register_intc_controller(&intc_desc_irq); 327 break; 328 default: 329 BUG(); 330 } 331 } 332 333 void __init plat_irq_setup(void) 334 { 335 register_intc_controller(&intc_desc); 336 } 337