1 /* 2 * SH7750/SH7751 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/serial_sci.h> 16 17 static struct resource rtc_resources[] = { 18 [0] = { 19 .start = 0xffc80000, 20 .end = 0xffc80000 + 0x58 - 1, 21 .flags = IORESOURCE_IO, 22 }, 23 [1] = { 24 /* Period IRQ */ 25 .start = 21, 26 .flags = IORESOURCE_IRQ, 27 }, 28 [2] = { 29 /* Carry IRQ */ 30 .start = 22, 31 .flags = IORESOURCE_IRQ, 32 }, 33 [3] = { 34 /* Alarm IRQ */ 35 .start = 20, 36 .flags = IORESOURCE_IRQ, 37 }, 38 }; 39 40 static struct platform_device rtc_device = { 41 .name = "sh-rtc", 42 .id = -1, 43 .num_resources = ARRAY_SIZE(rtc_resources), 44 .resource = rtc_resources, 45 }; 46 47 static struct plat_sci_port sci_platform_data[] = { 48 { 49 #ifndef CONFIG_SH_RTS7751R2D 50 .mapbase = 0xffe00000, 51 .flags = UPF_BOOT_AUTOCONF, 52 .type = PORT_SCI, 53 .irqs = { 23, 24, 25, 0 }, 54 }, { 55 #endif 56 .mapbase = 0xffe80000, 57 .flags = UPF_BOOT_AUTOCONF, 58 .type = PORT_SCIF, 59 .irqs = { 40, 41, 43, 42 }, 60 }, { 61 .flags = 0, 62 } 63 }; 64 65 static struct platform_device sci_device = { 66 .name = "sh-sci", 67 .id = -1, 68 .dev = { 69 .platform_data = sci_platform_data, 70 }, 71 }; 72 73 static struct platform_device *sh7750_devices[] __initdata = { 74 &rtc_device, 75 &sci_device, 76 }; 77 78 static int __init sh7750_devices_setup(void) 79 { 80 return platform_add_devices(sh7750_devices, 81 ARRAY_SIZE(sh7750_devices)); 82 } 83 __initcall(sh7750_devices_setup); 84 85 enum { 86 UNUSED = 0, 87 88 /* interrupt sources */ 89 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 90 HUDI, GPIOI, 91 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 92 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 93 DMAC_DMAE, 94 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 95 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 96 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 97 RTC_ATI, RTC_PRI, RTC_CUI, 98 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, 99 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, 100 WDT, 101 REF_RCMI, REF_ROVI, 102 103 /* interrupt groups */ 104 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 105 }; 106 107 static struct intc_vect vectors[] __initdata = { 108 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 109 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 110 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 111 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 112 INTC_VECT(RTC_CUI, 0x4c0), 113 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 114 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 115 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 116 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 117 INTC_VECT(WDT, 0x560), 118 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 119 }; 120 121 static struct intc_group groups[] __initdata = { 122 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 123 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 124 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), 125 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), 126 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 127 }; 128 129 static struct intc_prio_reg prio_registers[] __initdata = { 130 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 131 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 132 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 133 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 134 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 135 TMU4, TMU3, 136 PCIC1, PCIC0_PCISERR } }, 137 }; 138 139 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, 140 NULL, prio_registers, NULL); 141 142 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 143 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 144 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 145 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 146 defined(CONFIG_CPU_SUBTYPE_SH7091) 147 static struct intc_vect vectors_dma4[] __initdata = { 148 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 149 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 150 INTC_VECT(DMAC_DMAE, 0x6c0), 151 }; 152 153 static struct intc_group groups_dma4[] __initdata = { 154 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 155 DMAC_DMTE3, DMAC_DMAE), 156 }; 157 158 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 159 vectors_dma4, groups_dma4, 160 NULL, prio_registers, NULL); 161 #endif 162 163 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 164 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 165 static struct intc_vect vectors_dma8[] __initdata = { 166 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 167 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 168 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 169 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 170 INTC_VECT(DMAC_DMAE, 0x6c0), 171 }; 172 173 static struct intc_group groups_dma8[] __initdata = { 174 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 175 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 176 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 177 }; 178 179 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 180 vectors_dma8, groups_dma8, 181 NULL, prio_registers, NULL); 182 #endif 183 184 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 185 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 186 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 187 defined(CONFIG_CPU_SUBTYPE_SH7751R) 188 static struct intc_vect vectors_tmu34[] __initdata = { 189 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 190 }; 191 192 static struct intc_mask_reg mask_registers[] __initdata = { 193 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 194 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 195 0, 0, 0, 0, 0, 0, TMU4, TMU3, 196 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 197 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 198 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 199 }; 200 201 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 202 vectors_tmu34, NULL, 203 mask_registers, prio_registers, NULL); 204 #endif 205 206 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 207 static struct intc_vect vectors_irlm[] __initdata = { 208 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 209 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 210 }; 211 212 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 213 NULL, prio_registers, NULL); 214 215 /* SH7751 and SH7751R both have PCI */ 216 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 217 static struct intc_vect vectors_pci[] __initdata = { 218 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 219 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 220 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 221 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 222 }; 223 224 static struct intc_group groups_pci[] __initdata = { 225 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 226 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 227 }; 228 229 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 230 mask_registers, prio_registers, NULL); 231 #endif 232 233 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 234 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 235 defined(CONFIG_CPU_SUBTYPE_SH7091) 236 void __init plat_irq_setup(void) 237 { 238 /* 239 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 240 * see below.. 241 */ 242 register_intc_controller(&intc_desc); 243 register_intc_controller(&intc_desc_dma4); 244 } 245 #endif 246 247 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 248 void __init plat_irq_setup(void) 249 { 250 register_intc_controller(&intc_desc); 251 register_intc_controller(&intc_desc_dma8); 252 register_intc_controller(&intc_desc_tmu34); 253 } 254 #endif 255 256 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 257 void __init plat_irq_setup(void) 258 { 259 register_intc_controller(&intc_desc); 260 register_intc_controller(&intc_desc_dma4); 261 register_intc_controller(&intc_desc_tmu34); 262 register_intc_controller(&intc_desc_pci); 263 } 264 #endif 265 266 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 267 void __init plat_irq_setup(void) 268 { 269 register_intc_controller(&intc_desc); 270 register_intc_controller(&intc_desc_dma8); 271 register_intc_controller(&intc_desc_tmu34); 272 register_intc_controller(&intc_desc_pci); 273 } 274 #endif 275 276 #define INTC_ICR 0xffd00000UL 277 #define INTC_ICR_IRLM (1<<7) 278 279 void __init plat_irq_setup_pins(int mode) 280 { 281 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 282 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 283 return; 284 #endif 285 286 switch (mode) { 287 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 288 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 289 register_intc_controller(&intc_desc_irlm); 290 break; 291 default: 292 BUG(); 293 } 294 } 295