1 /* 2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/sh_timer.h> 16 #include <linux/sh_intc.h> 17 #include <linux/serial_sci.h> 18 #include <generated/machtypes.h> 19 20 static struct resource rtc_resources[] = { 21 [0] = { 22 .start = 0xffc80000, 23 .end = 0xffc80000 + 0x58 - 1, 24 .flags = IORESOURCE_IO, 25 }, 26 [1] = { 27 /* Shared Period/Carry/Alarm IRQ */ 28 .start = evt2irq(0x480), 29 .flags = IORESOURCE_IRQ, 30 }, 31 }; 32 33 static struct platform_device rtc_device = { 34 .name = "sh-rtc", 35 .id = -1, 36 .num_resources = ARRAY_SIZE(rtc_resources), 37 .resource = rtc_resources, 38 }; 39 40 static struct plat_sci_port sci_platform_data = { 41 .type = PORT_SCI, 42 .regshift = 2, 43 }; 44 45 static struct resource sci_resources[] = { 46 DEFINE_RES_MEM(0xffe00000, 0x100), 47 DEFINE_RES_IRQ(evt2irq(0x4e0)), 48 }; 49 50 static struct platform_device sci_device = { 51 .name = "sh-sci", 52 .id = 0, 53 .resource = sci_resources, 54 .num_resources = ARRAY_SIZE(sci_resources), 55 .dev = { 56 .platform_data = &sci_platform_data, 57 }, 58 }; 59 60 static struct plat_sci_port scif_platform_data = { 61 .scscr = SCSCR_REIE, 62 .type = PORT_SCIF, 63 }; 64 65 static struct resource scif_resources[] = { 66 DEFINE_RES_MEM(0xffe80000, 0x100), 67 DEFINE_RES_IRQ(evt2irq(0x700)), 68 }; 69 70 static struct platform_device scif_device = { 71 .name = "sh-sci", 72 .id = 1, 73 .resource = scif_resources, 74 .num_resources = ARRAY_SIZE(scif_resources), 75 .dev = { 76 .platform_data = &scif_platform_data, 77 }, 78 }; 79 80 static struct sh_timer_config tmu0_platform_data = { 81 .channels_mask = 7, 82 }; 83 84 static struct resource tmu0_resources[] = { 85 DEFINE_RES_MEM(0xffd80000, 0x30), 86 DEFINE_RES_IRQ(evt2irq(0x400)), 87 DEFINE_RES_IRQ(evt2irq(0x420)), 88 DEFINE_RES_IRQ(evt2irq(0x440)), 89 }; 90 91 static struct platform_device tmu0_device = { 92 .name = "sh-tmu", 93 .id = 0, 94 .dev = { 95 .platform_data = &tmu0_platform_data, 96 }, 97 .resource = tmu0_resources, 98 .num_resources = ARRAY_SIZE(tmu0_resources), 99 }; 100 101 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 102 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 103 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 104 defined(CONFIG_CPU_SUBTYPE_SH7751R) 105 106 static struct sh_timer_config tmu1_platform_data = { 107 .channels_mask = 3, 108 }; 109 110 static struct resource tmu1_resources[] = { 111 DEFINE_RES_MEM(0xfe100000, 0x20), 112 DEFINE_RES_IRQ(evt2irq(0xb00)), 113 DEFINE_RES_IRQ(evt2irq(0xb80)), 114 }; 115 116 static struct platform_device tmu1_device = { 117 .name = "sh-tmu", 118 .id = 1, 119 .dev = { 120 .platform_data = &tmu1_platform_data, 121 }, 122 .resource = tmu1_resources, 123 .num_resources = ARRAY_SIZE(tmu1_resources), 124 }; 125 126 #endif 127 128 static struct platform_device *sh7750_devices[] __initdata = { 129 &rtc_device, 130 &tmu0_device, 131 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 132 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 133 defined(CONFIG_CPU_SUBTYPE_SH7751R) 134 &tmu1_device, 135 #endif 136 }; 137 138 static int __init sh7750_devices_setup(void) 139 { 140 if (mach_is_rts7751r2d()) { 141 platform_device_register(&scif_device); 142 } else { 143 platform_device_register(&sci_device); 144 platform_device_register(&scif_device); 145 } 146 147 return platform_add_devices(sh7750_devices, 148 ARRAY_SIZE(sh7750_devices)); 149 } 150 arch_initcall(sh7750_devices_setup); 151 152 static struct platform_device *sh7750_early_devices[] __initdata = { 153 &tmu0_device, 154 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 155 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 156 defined(CONFIG_CPU_SUBTYPE_SH7751R) 157 &tmu1_device, 158 #endif 159 }; 160 161 void __init plat_early_device_setup(void) 162 { 163 struct platform_device *dev[1]; 164 165 if (mach_is_rts7751r2d()) { 166 scif_platform_data.scscr |= SCSCR_CKE1; 167 dev[0] = &scif_device; 168 early_platform_add_devices(dev, 1); 169 } else { 170 dev[0] = &sci_device; 171 early_platform_add_devices(dev, 1); 172 dev[0] = &scif_device; 173 early_platform_add_devices(dev, 1); 174 } 175 176 early_platform_add_devices(sh7750_early_devices, 177 ARRAY_SIZE(sh7750_early_devices)); 178 } 179 180 enum { 181 UNUSED = 0, 182 183 /* interrupt sources */ 184 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 185 HUDI, GPIOI, DMAC, 186 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 187 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 188 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 189 190 /* interrupt groups */ 191 PCIC1, 192 }; 193 194 static struct intc_vect vectors[] __initdata = { 195 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 196 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 197 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 198 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 199 INTC_VECT(RTC, 0x4c0), 200 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 201 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 202 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 203 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 204 INTC_VECT(WDT, 0x560), 205 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 206 }; 207 208 static struct intc_prio_reg prio_registers[] __initdata = { 209 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 210 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 211 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 212 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 213 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 214 TMU4, TMU3, 215 PCIC1, PCIC0_PCISERR } }, 216 }; 217 218 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 219 NULL, prio_registers, NULL); 220 221 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 222 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 223 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 224 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 225 defined(CONFIG_CPU_SUBTYPE_SH7091) 226 static struct intc_vect vectors_dma4[] __initdata = { 227 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 228 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 229 INTC_VECT(DMAC, 0x6c0), 230 }; 231 232 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 233 vectors_dma4, NULL, 234 NULL, prio_registers, NULL); 235 #endif 236 237 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 238 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 239 static struct intc_vect vectors_dma8[] __initdata = { 240 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 241 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 242 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 243 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 244 INTC_VECT(DMAC, 0x6c0), 245 }; 246 247 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 248 vectors_dma8, NULL, 249 NULL, prio_registers, NULL); 250 #endif 251 252 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 253 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 254 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 255 defined(CONFIG_CPU_SUBTYPE_SH7751R) 256 static struct intc_vect vectors_tmu34[] __initdata = { 257 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 258 }; 259 260 static struct intc_mask_reg mask_registers[] __initdata = { 261 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 262 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 263 0, 0, 0, 0, 0, 0, TMU4, TMU3, 264 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 265 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 266 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 267 }; 268 269 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 270 vectors_tmu34, NULL, 271 mask_registers, prio_registers, NULL); 272 #endif 273 274 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 275 static struct intc_vect vectors_irlm[] __initdata = { 276 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 277 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 278 }; 279 280 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 281 NULL, prio_registers, NULL); 282 283 /* SH7751 and SH7751R both have PCI */ 284 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 285 static struct intc_vect vectors_pci[] __initdata = { 286 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 287 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 288 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 289 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 290 }; 291 292 static struct intc_group groups_pci[] __initdata = { 293 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 294 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 295 }; 296 297 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 298 mask_registers, prio_registers, NULL); 299 #endif 300 301 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 302 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 303 defined(CONFIG_CPU_SUBTYPE_SH7091) 304 void __init plat_irq_setup(void) 305 { 306 /* 307 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 308 * see below.. 309 */ 310 register_intc_controller(&intc_desc); 311 register_intc_controller(&intc_desc_dma4); 312 } 313 #endif 314 315 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 316 void __init plat_irq_setup(void) 317 { 318 register_intc_controller(&intc_desc); 319 register_intc_controller(&intc_desc_dma8); 320 register_intc_controller(&intc_desc_tmu34); 321 } 322 #endif 323 324 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 325 void __init plat_irq_setup(void) 326 { 327 register_intc_controller(&intc_desc); 328 register_intc_controller(&intc_desc_dma4); 329 register_intc_controller(&intc_desc_tmu34); 330 register_intc_controller(&intc_desc_pci); 331 } 332 #endif 333 334 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 335 void __init plat_irq_setup(void) 336 { 337 register_intc_controller(&intc_desc); 338 register_intc_controller(&intc_desc_dma8); 339 register_intc_controller(&intc_desc_tmu34); 340 register_intc_controller(&intc_desc_pci); 341 } 342 #endif 343 344 #define INTC_ICR 0xffd00000UL 345 #define INTC_ICR_IRLM (1<<7) 346 347 void __init plat_irq_setup_pins(int mode) 348 { 349 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 350 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 351 return; 352 #endif 353 354 switch (mode) { 355 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 356 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 357 register_intc_controller(&intc_desc_irlm); 358 break; 359 default: 360 BUG(); 361 } 362 } 363