1 /* 2 * SH7750/SH7751 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/serial_sci.h> 16 17 static struct resource rtc_resources[] = { 18 [0] = { 19 .start = 0xffc80000, 20 .end = 0xffc80000 + 0x58 - 1, 21 .flags = IORESOURCE_IO, 22 }, 23 [1] = { 24 /* Shared Period/Carry/Alarm IRQ */ 25 .start = 20, 26 .flags = IORESOURCE_IRQ, 27 }, 28 }; 29 30 static struct platform_device rtc_device = { 31 .name = "sh-rtc", 32 .id = -1, 33 .num_resources = ARRAY_SIZE(rtc_resources), 34 .resource = rtc_resources, 35 }; 36 37 static struct plat_sci_port sci_platform_data[] = { 38 { 39 #ifndef CONFIG_SH_RTS7751R2D 40 .mapbase = 0xffe00000, 41 .flags = UPF_BOOT_AUTOCONF, 42 .type = PORT_SCI, 43 .irqs = { 23, 23, 23, 0 }, 44 }, { 45 #endif 46 .mapbase = 0xffe80000, 47 .flags = UPF_BOOT_AUTOCONF, 48 .type = PORT_SCIF, 49 .irqs = { 40, 40, 40, 40 }, 50 }, { 51 .flags = 0, 52 } 53 }; 54 55 static struct platform_device sci_device = { 56 .name = "sh-sci", 57 .id = -1, 58 .dev = { 59 .platform_data = sci_platform_data, 60 }, 61 }; 62 63 static struct platform_device *sh7750_devices[] __initdata = { 64 &rtc_device, 65 &sci_device, 66 }; 67 68 static int __init sh7750_devices_setup(void) 69 { 70 return platform_add_devices(sh7750_devices, 71 ARRAY_SIZE(sh7750_devices)); 72 } 73 __initcall(sh7750_devices_setup); 74 75 enum { 76 UNUSED = 0, 77 78 /* interrupt sources */ 79 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 80 HUDI, GPIOI, DMAC, 81 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 82 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 83 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 84 85 /* interrupt groups */ 86 PCIC1, 87 }; 88 89 static struct intc_vect vectors[] __initdata = { 90 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 91 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 92 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 93 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 94 INTC_VECT(RTC, 0x4c0), 95 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 96 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 97 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 98 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 99 INTC_VECT(WDT, 0x560), 100 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 101 }; 102 103 static struct intc_prio_reg prio_registers[] __initdata = { 104 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 106 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 107 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 108 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 109 TMU4, TMU3, 110 PCIC1, PCIC0_PCISERR } }, 111 }; 112 113 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 114 NULL, prio_registers, NULL); 115 116 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 117 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 118 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 119 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 120 defined(CONFIG_CPU_SUBTYPE_SH7091) 121 static struct intc_vect vectors_dma4[] __initdata = { 122 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 123 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 124 INTC_VECT(DMAC, 0x6c0), 125 }; 126 127 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 128 vectors_dma4, NULL, 129 NULL, prio_registers, NULL); 130 #endif 131 132 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 133 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 134 static struct intc_vect vectors_dma8[] __initdata = { 135 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 136 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 137 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 138 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 139 INTC_VECT(DMAC, 0x6c0), 140 }; 141 142 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 143 vectors_dma8, NULL, 144 NULL, prio_registers, NULL); 145 #endif 146 147 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 148 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 149 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 150 defined(CONFIG_CPU_SUBTYPE_SH7751R) 151 static struct intc_vect vectors_tmu34[] __initdata = { 152 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 153 }; 154 155 static struct intc_mask_reg mask_registers[] __initdata = { 156 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 157 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 158 0, 0, 0, 0, 0, 0, TMU4, TMU3, 159 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 160 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 161 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 162 }; 163 164 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 165 vectors_tmu34, NULL, 166 mask_registers, prio_registers, NULL); 167 #endif 168 169 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 170 static struct intc_vect vectors_irlm[] __initdata = { 171 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 172 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 173 }; 174 175 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 176 NULL, prio_registers, NULL); 177 178 /* SH7751 and SH7751R both have PCI */ 179 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 180 static struct intc_vect vectors_pci[] __initdata = { 181 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 182 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 183 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 184 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 185 }; 186 187 static struct intc_group groups_pci[] __initdata = { 188 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 189 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 190 }; 191 192 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 193 mask_registers, prio_registers, NULL); 194 #endif 195 196 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 197 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 198 defined(CONFIG_CPU_SUBTYPE_SH7091) 199 void __init plat_irq_setup(void) 200 { 201 /* 202 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 203 * see below.. 204 */ 205 register_intc_controller(&intc_desc); 206 register_intc_controller(&intc_desc_dma4); 207 } 208 #endif 209 210 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 211 void __init plat_irq_setup(void) 212 { 213 register_intc_controller(&intc_desc); 214 register_intc_controller(&intc_desc_dma8); 215 register_intc_controller(&intc_desc_tmu34); 216 } 217 #endif 218 219 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 220 void __init plat_irq_setup(void) 221 { 222 register_intc_controller(&intc_desc); 223 register_intc_controller(&intc_desc_dma4); 224 register_intc_controller(&intc_desc_tmu34); 225 register_intc_controller(&intc_desc_pci); 226 } 227 #endif 228 229 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 230 void __init plat_irq_setup(void) 231 { 232 register_intc_controller(&intc_desc); 233 register_intc_controller(&intc_desc_dma8); 234 register_intc_controller(&intc_desc_tmu34); 235 register_intc_controller(&intc_desc_pci); 236 } 237 #endif 238 239 #define INTC_ICR 0xffd00000UL 240 #define INTC_ICR_IRLM (1<<7) 241 242 void __init plat_irq_setup_pins(int mode) 243 { 244 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 245 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 246 return; 247 #endif 248 249 switch (mode) { 250 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 251 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 252 register_intc_controller(&intc_desc_irlm); 253 break; 254 default: 255 BUG(); 256 } 257 } 258