1 /* 2 * SH7750/SH7751 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <asm/sci.h> 16 17 static struct resource rtc_resources[] = { 18 [0] = { 19 .start = 0xffc80000, 20 .end = 0xffc80000 + 0x58 - 1, 21 .flags = IORESOURCE_IO, 22 }, 23 [1] = { 24 /* Period IRQ */ 25 .start = 21, 26 .flags = IORESOURCE_IRQ, 27 }, 28 [2] = { 29 /* Carry IRQ */ 30 .start = 22, 31 .flags = IORESOURCE_IRQ, 32 }, 33 [3] = { 34 /* Alarm IRQ */ 35 .start = 20, 36 .flags = IORESOURCE_IRQ, 37 }, 38 }; 39 40 static struct platform_device rtc_device = { 41 .name = "sh-rtc", 42 .id = -1, 43 .num_resources = ARRAY_SIZE(rtc_resources), 44 .resource = rtc_resources, 45 }; 46 47 static struct plat_sci_port sci_platform_data[] = { 48 { 49 #ifndef CONFIG_SH_RTS7751R2D 50 .mapbase = 0xffe00000, 51 .flags = UPF_BOOT_AUTOCONF, 52 .type = PORT_SCI, 53 .irqs = { 23, 24, 25, 0 }, 54 }, { 55 #endif 56 .mapbase = 0xffe80000, 57 .flags = UPF_BOOT_AUTOCONF, 58 .type = PORT_SCIF, 59 .irqs = { 40, 41, 43, 42 }, 60 }, { 61 .flags = 0, 62 } 63 }; 64 65 static struct platform_device sci_device = { 66 .name = "sh-sci", 67 .id = -1, 68 .dev = { 69 .platform_data = sci_platform_data, 70 }, 71 }; 72 73 static struct platform_device *sh7750_devices[] __initdata = { 74 &rtc_device, 75 &sci_device, 76 }; 77 78 static int __init sh7750_devices_setup(void) 79 { 80 return platform_add_devices(sh7750_devices, 81 ARRAY_SIZE(sh7750_devices)); 82 } 83 __initcall(sh7750_devices_setup); 84 85 static struct ipr_data sh7750_ipr_map[] = { 86 /* IRQ, IPR-idx, shift, priority */ 87 { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 88 { 17, 0, 12, 2 }, /* TMU1 TUNI */ 89 { 18, 0, 4, 2 }, /* TMU2 TUNI */ 90 { 19, 0, 4, 2 }, /* TMU2 TIPCI */ 91 { 27, 1, 12, 2 }, /* WDT ITI */ 92 { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ 93 { 21, 0, 0, 2 }, /* RTC PRI (period) */ 94 { 22, 0, 0, 2 }, /* RTC CUI (carry) */ 95 { 23, 1, 4, 3 }, /* SCI ERI */ 96 { 24, 1, 4, 3 }, /* SCI RXI */ 97 { 25, 1, 4, 3 }, /* SCI TXI */ 98 { 40, 2, 4, 3 }, /* SCIF ERI */ 99 { 41, 2, 4, 3 }, /* SCIF RXI */ 100 { 42, 2, 4, 3 }, /* SCIF BRI */ 101 { 43, 2, 4, 3 }, /* SCIF TXI */ 102 { 34, 2, 8, 7 }, /* DMAC DMTE0 */ 103 { 35, 2, 8, 7 }, /* DMAC DMTE1 */ 104 { 36, 2, 8, 7 }, /* DMAC DMTE2 */ 105 { 37, 2, 8, 7 }, /* DMAC DMTE3 */ 106 { 38, 2, 8, 7 }, /* DMAC DMAE */ 107 }; 108 109 #ifdef CONFIG_CPU_SUBTYPE_SH7751 110 static struct ipr_data sh7751_ipr_map[] = { 111 { 44, 2, 8, 7 }, /* DMAC DMTE4 */ 112 { 45, 2, 8, 7 }, /* DMAC DMTE5 */ 113 { 46, 2, 8, 7 }, /* DMAC DMTE6 */ 114 { 47, 2, 8, 7 }, /* DMAC DMTE7 */ 115 /* The following use INTC_INPRI00 for masking, which is a 32-bit 116 register, not a 16-bit register like the IPRx registers, so it 117 would need special support */ 118 /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */ 119 /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */ 120 }; 121 #endif 122 123 static unsigned long ipr_offsets[] = { 124 0xffd00004UL, /* 0: IPRA */ 125 0xffd00008UL, /* 1: IPRB */ 126 0xffd0000cUL, /* 2: IPRC */ 127 0xffd00010UL, /* 3: IPRD */ 128 }; 129 130 /* given the IPR index return the address of the IPR register */ 131 unsigned int map_ipridx_to_addr(int idx) 132 { 133 if (idx >= ARRAY_SIZE(ipr_offsets)) 134 return 0; 135 return ipr_offsets[idx]; 136 } 137 138 #define INTC_ICR 0xffd00000UL 139 #define INTC_ICR_IRLM (1<<7) 140 141 /* enable individual interrupt mode for external interupts */ 142 void ipr_irq_enable_irlm(void) 143 { 144 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 145 } 146 147 void __init init_IRQ_ipr() 148 { 149 make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map)); 150 #ifdef CONFIG_CPU_SUBTYPE_SH7751 151 make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map)); 152 #endif 153 } 154