1 /* 2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/sh_timer.h> 16 #include <linux/serial_sci.h> 17 #include <generated/machtypes.h> 18 19 static struct resource rtc_resources[] = { 20 [0] = { 21 .start = 0xffc80000, 22 .end = 0xffc80000 + 0x58 - 1, 23 .flags = IORESOURCE_IO, 24 }, 25 [1] = { 26 /* Shared Period/Carry/Alarm IRQ */ 27 .start = 20, 28 .flags = IORESOURCE_IRQ, 29 }, 30 }; 31 32 static struct platform_device rtc_device = { 33 .name = "sh-rtc", 34 .id = -1, 35 .num_resources = ARRAY_SIZE(rtc_resources), 36 .resource = rtc_resources, 37 }; 38 39 static struct plat_sci_port sci_platform_data = { 40 .mapbase = 0xffe00000, 41 .port_reg = 0xffe0001C 42 .flags = UPF_BOOT_AUTOCONF, 43 .scscr = SCSCR_TE | SCSCR_RE, 44 .scbrr_algo_id = SCBRR_ALGO_2, 45 .type = PORT_SCI, 46 .irqs = { 23, 23, 23, 0 }, 47 .regshift = 2, 48 }; 49 50 static struct platform_device sci_device = { 51 .name = "sh-sci", 52 .id = 0, 53 .dev = { 54 .platform_data = &sci_platform_data, 55 }, 56 }; 57 58 static struct plat_sci_port scif_platform_data = { 59 .mapbase = 0xffe80000, 60 .flags = UPF_BOOT_AUTOCONF, 61 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 62 .scbrr_algo_id = SCBRR_ALGO_2, 63 .type = PORT_SCIF, 64 .irqs = { 40, 40, 40, 40 }, 65 }; 66 67 static struct platform_device scif_device = { 68 .name = "sh-sci", 69 .id = 1, 70 .dev = { 71 .platform_data = &scif_platform_data, 72 }, 73 }; 74 75 static struct sh_timer_config tmu0_platform_data = { 76 .channel_offset = 0x04, 77 .timer_bit = 0, 78 .clockevent_rating = 200, 79 }; 80 81 static struct resource tmu0_resources[] = { 82 [0] = { 83 .start = 0xffd80008, 84 .end = 0xffd80013, 85 .flags = IORESOURCE_MEM, 86 }, 87 [1] = { 88 .start = 16, 89 .flags = IORESOURCE_IRQ, 90 }, 91 }; 92 93 static struct platform_device tmu0_device = { 94 .name = "sh_tmu", 95 .id = 0, 96 .dev = { 97 .platform_data = &tmu0_platform_data, 98 }, 99 .resource = tmu0_resources, 100 .num_resources = ARRAY_SIZE(tmu0_resources), 101 }; 102 103 static struct sh_timer_config tmu1_platform_data = { 104 .channel_offset = 0x10, 105 .timer_bit = 1, 106 .clocksource_rating = 200, 107 }; 108 109 static struct resource tmu1_resources[] = { 110 [0] = { 111 .start = 0xffd80014, 112 .end = 0xffd8001f, 113 .flags = IORESOURCE_MEM, 114 }, 115 [1] = { 116 .start = 17, 117 .flags = IORESOURCE_IRQ, 118 }, 119 }; 120 121 static struct platform_device tmu1_device = { 122 .name = "sh_tmu", 123 .id = 1, 124 .dev = { 125 .platform_data = &tmu1_platform_data, 126 }, 127 .resource = tmu1_resources, 128 .num_resources = ARRAY_SIZE(tmu1_resources), 129 }; 130 131 static struct sh_timer_config tmu2_platform_data = { 132 .channel_offset = 0x1c, 133 .timer_bit = 2, 134 }; 135 136 static struct resource tmu2_resources[] = { 137 [0] = { 138 .start = 0xffd80020, 139 .end = 0xffd8002f, 140 .flags = IORESOURCE_MEM, 141 }, 142 [1] = { 143 .start = 18, 144 .flags = IORESOURCE_IRQ, 145 }, 146 }; 147 148 static struct platform_device tmu2_device = { 149 .name = "sh_tmu", 150 .id = 2, 151 .dev = { 152 .platform_data = &tmu2_platform_data, 153 }, 154 .resource = tmu2_resources, 155 .num_resources = ARRAY_SIZE(tmu2_resources), 156 }; 157 158 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 159 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 160 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 161 defined(CONFIG_CPU_SUBTYPE_SH7751R) 162 163 static struct sh_timer_config tmu3_platform_data = { 164 .channel_offset = 0x04, 165 .timer_bit = 0, 166 }; 167 168 static struct resource tmu3_resources[] = { 169 [0] = { 170 .start = 0xfe100008, 171 .end = 0xfe100013, 172 .flags = IORESOURCE_MEM, 173 }, 174 [1] = { 175 .start = 72, 176 .flags = IORESOURCE_IRQ, 177 }, 178 }; 179 180 static struct platform_device tmu3_device = { 181 .name = "sh_tmu", 182 .id = 3, 183 .dev = { 184 .platform_data = &tmu3_platform_data, 185 }, 186 .resource = tmu3_resources, 187 .num_resources = ARRAY_SIZE(tmu3_resources), 188 }; 189 190 static struct sh_timer_config tmu4_platform_data = { 191 .channel_offset = 0x10, 192 .timer_bit = 1, 193 }; 194 195 static struct resource tmu4_resources[] = { 196 [0] = { 197 .start = 0xfe100014, 198 .end = 0xfe10001f, 199 .flags = IORESOURCE_MEM, 200 }, 201 [1] = { 202 .start = 76, 203 .flags = IORESOURCE_IRQ, 204 }, 205 }; 206 207 static struct platform_device tmu4_device = { 208 .name = "sh_tmu", 209 .id = 4, 210 .dev = { 211 .platform_data = &tmu4_platform_data, 212 }, 213 .resource = tmu4_resources, 214 .num_resources = ARRAY_SIZE(tmu4_resources), 215 }; 216 217 #endif 218 219 static struct platform_device *sh7750_devices[] __initdata = { 220 &rtc_device, 221 &tmu0_device, 222 &tmu1_device, 223 &tmu2_device, 224 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 225 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 226 defined(CONFIG_CPU_SUBTYPE_SH7751R) 227 &tmu3_device, 228 &tmu4_device, 229 #endif 230 }; 231 232 static int __init sh7750_devices_setup(void) 233 { 234 if (mach_is_rts7751r2d()) { 235 platform_device_register(&scif_device); 236 } else { 237 platform_device_register(&sci_device); 238 platform_device_register(&scif_device); 239 } 240 241 return platform_add_devices(sh7750_devices, 242 ARRAY_SIZE(sh7750_devices)); 243 } 244 arch_initcall(sh7750_devices_setup); 245 246 static struct platform_device *sh7750_early_devices[] __initdata = { 247 &tmu0_device, 248 &tmu1_device, 249 &tmu2_device, 250 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 251 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 252 defined(CONFIG_CPU_SUBTYPE_SH7751R) 253 &tmu3_device, 254 &tmu4_device, 255 #endif 256 }; 257 258 void __init plat_early_device_setup(void) 259 { 260 struct platform_device *dev[1]; 261 262 if (mach_is_rts7751r2d()) { 263 scif_platform_data.scscr |= SCSCR_CKE1; 264 dev[0] = &scif_device; 265 early_platform_add_devices(dev, 1); 266 } else { 267 dev[0] = &sci_device; 268 early_platform_add_devices(dev, 1); 269 dev[0] = &scif_device; 270 early_platform_add_devices(dev, 1); 271 } 272 273 early_platform_add_devices(sh7750_early_devices, 274 ARRAY_SIZE(sh7750_early_devices)); 275 } 276 277 enum { 278 UNUSED = 0, 279 280 /* interrupt sources */ 281 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 282 HUDI, GPIOI, DMAC, 283 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 284 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 285 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 286 287 /* interrupt groups */ 288 PCIC1, 289 }; 290 291 static struct intc_vect vectors[] __initdata = { 292 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 293 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 294 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 295 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 296 INTC_VECT(RTC, 0x4c0), 297 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 298 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 299 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 300 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 301 INTC_VECT(WDT, 0x560), 302 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 303 }; 304 305 static struct intc_prio_reg prio_registers[] __initdata = { 306 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 307 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 308 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 309 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 310 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 311 TMU4, TMU3, 312 PCIC1, PCIC0_PCISERR } }, 313 }; 314 315 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 316 NULL, prio_registers, NULL); 317 318 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 319 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 320 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 321 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 322 defined(CONFIG_CPU_SUBTYPE_SH7091) 323 static struct intc_vect vectors_dma4[] __initdata = { 324 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 325 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 326 INTC_VECT(DMAC, 0x6c0), 327 }; 328 329 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 330 vectors_dma4, NULL, 331 NULL, prio_registers, NULL); 332 #endif 333 334 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 335 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 336 static struct intc_vect vectors_dma8[] __initdata = { 337 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 338 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 339 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 340 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 341 INTC_VECT(DMAC, 0x6c0), 342 }; 343 344 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 345 vectors_dma8, NULL, 346 NULL, prio_registers, NULL); 347 #endif 348 349 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 350 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 351 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 352 defined(CONFIG_CPU_SUBTYPE_SH7751R) 353 static struct intc_vect vectors_tmu34[] __initdata = { 354 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 355 }; 356 357 static struct intc_mask_reg mask_registers[] __initdata = { 358 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 359 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 360 0, 0, 0, 0, 0, 0, TMU4, TMU3, 361 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 362 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 363 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 364 }; 365 366 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 367 vectors_tmu34, NULL, 368 mask_registers, prio_registers, NULL); 369 #endif 370 371 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 372 static struct intc_vect vectors_irlm[] __initdata = { 373 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 374 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 375 }; 376 377 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 378 NULL, prio_registers, NULL); 379 380 /* SH7751 and SH7751R both have PCI */ 381 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 382 static struct intc_vect vectors_pci[] __initdata = { 383 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 384 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 385 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 386 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 387 }; 388 389 static struct intc_group groups_pci[] __initdata = { 390 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 391 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 392 }; 393 394 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 395 mask_registers, prio_registers, NULL); 396 #endif 397 398 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 399 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 400 defined(CONFIG_CPU_SUBTYPE_SH7091) 401 void __init plat_irq_setup(void) 402 { 403 /* 404 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 405 * see below.. 406 */ 407 register_intc_controller(&intc_desc); 408 register_intc_controller(&intc_desc_dma4); 409 } 410 #endif 411 412 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 413 void __init plat_irq_setup(void) 414 { 415 register_intc_controller(&intc_desc); 416 register_intc_controller(&intc_desc_dma8); 417 register_intc_controller(&intc_desc_tmu34); 418 } 419 #endif 420 421 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 422 void __init plat_irq_setup(void) 423 { 424 register_intc_controller(&intc_desc); 425 register_intc_controller(&intc_desc_dma4); 426 register_intc_controller(&intc_desc_tmu34); 427 register_intc_controller(&intc_desc_pci); 428 } 429 #endif 430 431 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 432 void __init plat_irq_setup(void) 433 { 434 register_intc_controller(&intc_desc); 435 register_intc_controller(&intc_desc_dma8); 436 register_intc_controller(&intc_desc_tmu34); 437 register_intc_controller(&intc_desc_pci); 438 } 439 #endif 440 441 #define INTC_ICR 0xffd00000UL 442 #define INTC_ICR_IRLM (1<<7) 443 444 void __init plat_irq_setup_pins(int mode) 445 { 446 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 447 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 448 return; 449 #endif 450 451 switch (mode) { 452 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 453 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 454 register_intc_controller(&intc_desc_irlm); 455 break; 456 default: 457 BUG(); 458 } 459 } 460