1 /* 2 * SH7750/SH7751 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/io.h> 15 #include <linux/sh_timer.h> 16 #include <linux/serial_sci.h> 17 #include <asm/machtypes.h> 18 19 static struct resource rtc_resources[] = { 20 [0] = { 21 .start = 0xffc80000, 22 .end = 0xffc80000 + 0x58 - 1, 23 .flags = IORESOURCE_IO, 24 }, 25 [1] = { 26 /* Shared Period/Carry/Alarm IRQ */ 27 .start = 20, 28 .flags = IORESOURCE_IRQ, 29 }, 30 }; 31 32 static struct platform_device rtc_device = { 33 .name = "sh-rtc", 34 .id = -1, 35 .num_resources = ARRAY_SIZE(rtc_resources), 36 .resource = rtc_resources, 37 }; 38 39 static struct plat_sci_port sci_platform_data = { 40 .mapbase = 0xffe00000, 41 .flags = UPF_BOOT_AUTOCONF, 42 .type = PORT_SCI, 43 .scscr = SCSCR_TE | SCSCR_RE, 44 .irqs = { 23, 23, 23, 0 }, 45 }; 46 47 static struct platform_device sci_device = { 48 .name = "sh-sci", 49 .dev = { 50 .platform_data = sci_platform_data, 51 }, 52 }; 53 54 static struct plat_sci_port scif_platform_data = { 55 .mapbase = 0xffe80000, 56 .flags = UPF_BOOT_AUTOCONF, 57 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 58 .type = PORT_SCIF, 59 .irqs = { 40, 40, 40, 40 }, 60 }; 61 62 static struct platform_device scif_device = { 63 .name = "sh-sci", 64 .dev = { 65 .platform_data = scif_platform_data, 66 }, 67 }; 68 69 static struct sh_timer_config tmu0_platform_data = { 70 .name = "TMU0", 71 .channel_offset = 0x04, 72 .timer_bit = 0, 73 .clk = "peripheral_clk", 74 .clockevent_rating = 200, 75 }; 76 77 static struct resource tmu0_resources[] = { 78 [0] = { 79 .name = "TMU0", 80 .start = 0xffd80008, 81 .end = 0xffd80013, 82 .flags = IORESOURCE_MEM, 83 }, 84 [1] = { 85 .start = 16, 86 .flags = IORESOURCE_IRQ, 87 }, 88 }; 89 90 static struct platform_device tmu0_device = { 91 .name = "sh_tmu", 92 .id = 0, 93 .dev = { 94 .platform_data = &tmu0_platform_data, 95 }, 96 .resource = tmu0_resources, 97 .num_resources = ARRAY_SIZE(tmu0_resources), 98 }; 99 100 static struct sh_timer_config tmu1_platform_data = { 101 .name = "TMU1", 102 .channel_offset = 0x10, 103 .timer_bit = 1, 104 .clk = "peripheral_clk", 105 .clocksource_rating = 200, 106 }; 107 108 static struct resource tmu1_resources[] = { 109 [0] = { 110 .name = "TMU1", 111 .start = 0xffd80014, 112 .end = 0xffd8001f, 113 .flags = IORESOURCE_MEM, 114 }, 115 [1] = { 116 .start = 17, 117 .flags = IORESOURCE_IRQ, 118 }, 119 }; 120 121 static struct platform_device tmu1_device = { 122 .name = "sh_tmu", 123 .id = 1, 124 .dev = { 125 .platform_data = &tmu1_platform_data, 126 }, 127 .resource = tmu1_resources, 128 .num_resources = ARRAY_SIZE(tmu1_resources), 129 }; 130 131 static struct sh_timer_config tmu2_platform_data = { 132 .name = "TMU2", 133 .channel_offset = 0x1c, 134 .timer_bit = 2, 135 .clk = "peripheral_clk", 136 }; 137 138 static struct resource tmu2_resources[] = { 139 [0] = { 140 .name = "TMU2", 141 .start = 0xffd80020, 142 .end = 0xffd8002f, 143 .flags = IORESOURCE_MEM, 144 }, 145 [1] = { 146 .start = 18, 147 .flags = IORESOURCE_IRQ, 148 }, 149 }; 150 151 static struct platform_device tmu2_device = { 152 .name = "sh_tmu", 153 .id = 2, 154 .dev = { 155 .platform_data = &tmu2_platform_data, 156 }, 157 .resource = tmu2_resources, 158 .num_resources = ARRAY_SIZE(tmu2_resources), 159 }; 160 161 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 162 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 163 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 164 defined(CONFIG_CPU_SUBTYPE_SH7751R) 165 166 static struct sh_timer_config tmu3_platform_data = { 167 .name = "TMU3", 168 .channel_offset = 0x04, 169 .timer_bit = 0, 170 .clk = "peripheral_clk", 171 }; 172 173 static struct resource tmu3_resources[] = { 174 [0] = { 175 .name = "TMU3", 176 .start = 0xfe100008, 177 .end = 0xfe100013, 178 .flags = IORESOURCE_MEM, 179 }, 180 [1] = { 181 .start = 72, 182 .flags = IORESOURCE_IRQ, 183 }, 184 }; 185 186 static struct platform_device tmu3_device = { 187 .name = "sh_tmu", 188 .id = 3, 189 .dev = { 190 .platform_data = &tmu3_platform_data, 191 }, 192 .resource = tmu3_resources, 193 .num_resources = ARRAY_SIZE(tmu3_resources), 194 }; 195 196 static struct sh_timer_config tmu4_platform_data = { 197 .name = "TMU4", 198 .channel_offset = 0x10, 199 .timer_bit = 1, 200 .clk = "peripheral_clk", 201 }; 202 203 static struct resource tmu4_resources[] = { 204 [0] = { 205 .name = "TMU4", 206 .start = 0xfe100014, 207 .end = 0xfe10001f, 208 .flags = IORESOURCE_MEM, 209 }, 210 [1] = { 211 .start = 76, 212 .flags = IORESOURCE_IRQ, 213 }, 214 }; 215 216 static struct platform_device tmu4_device = { 217 .name = "sh_tmu", 218 .id = 4, 219 .dev = { 220 .platform_data = &tmu4_platform_data, 221 }, 222 .resource = tmu4_resources, 223 .num_resources = ARRAY_SIZE(tmu4_resources), 224 }; 225 226 #endif 227 228 static struct platform_device *sh7750_devices[] __initdata = { 229 &rtc_device, 230 &tmu0_device, 231 &tmu1_device, 232 &tmu2_device, 233 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 234 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 235 defined(CONFIG_CPU_SUBTYPE_SH7751R) 236 &tmu3_device, 237 &tmu4_device, 238 #endif 239 }; 240 241 static int __init sh7750_devices_setup(void) 242 { 243 if (mach_is_rts7751r2d()) { 244 scif_platform_data.scscr |= SCSCR_CKE1; 245 platform_register_device(&scif_device); 246 } else { 247 platform_register_device(&sci_device); 248 platform_register_device(&scif_device); 249 } 250 251 return platform_add_devices(sh7750_devices, 252 ARRAY_SIZE(sh7750_devices)); 253 } 254 __initcall(sh7750_devices_setup); 255 256 static struct platform_device *sh7750_early_devices[] __initdata = { 257 &tmu0_device, 258 &tmu1_device, 259 &tmu2_device, 260 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 261 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 262 defined(CONFIG_CPU_SUBTYPE_SH7751R) 263 &tmu3_device, 264 &tmu4_device, 265 #endif 266 }; 267 268 void __init plat_early_device_setup(void) 269 { 270 early_platform_add_devices(sh7750_early_devices, 271 ARRAY_SIZE(sh7750_early_devices)); 272 } 273 274 enum { 275 UNUSED = 0, 276 277 /* interrupt sources */ 278 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 279 HUDI, GPIOI, DMAC, 280 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 281 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 282 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, 283 284 /* interrupt groups */ 285 PCIC1, 286 }; 287 288 static struct intc_vect vectors[] __initdata = { 289 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 290 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 291 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 292 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 293 INTC_VECT(RTC, 0x4c0), 294 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500), 295 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540), 296 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 297 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 298 INTC_VECT(WDT, 0x560), 299 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0), 300 }; 301 302 static struct intc_prio_reg prio_registers[] __initdata = { 303 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 304 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 305 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 306 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 307 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, 308 TMU4, TMU3, 309 PCIC1, PCIC0_PCISERR } }, 310 }; 311 312 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL, 313 NULL, prio_registers, NULL); 314 315 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 316 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 317 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 318 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 319 defined(CONFIG_CPU_SUBTYPE_SH7091) 320 static struct intc_vect vectors_dma4[] __initdata = { 321 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 322 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 323 INTC_VECT(DMAC, 0x6c0), 324 }; 325 326 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 327 vectors_dma4, NULL, 328 NULL, prio_registers, NULL); 329 #endif 330 331 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 332 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 333 static struct intc_vect vectors_dma8[] __initdata = { 334 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660), 335 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0), 336 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0), 337 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0), 338 INTC_VECT(DMAC, 0x6c0), 339 }; 340 341 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 342 vectors_dma8, NULL, 343 NULL, prio_registers, NULL); 344 #endif 345 346 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 347 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ 348 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 349 defined(CONFIG_CPU_SUBTYPE_SH7751R) 350 static struct intc_vect vectors_tmu34[] __initdata = { 351 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 352 }; 353 354 static struct intc_mask_reg mask_registers[] __initdata = { 355 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 356 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 357 0, 0, 0, 0, 0, 0, TMU4, TMU3, 358 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 359 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 360 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 361 }; 362 363 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", 364 vectors_tmu34, NULL, 365 mask_registers, prio_registers, NULL); 366 #endif 367 368 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 369 static struct intc_vect vectors_irlm[] __initdata = { 370 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 371 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 372 }; 373 374 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, 375 NULL, prio_registers, NULL); 376 377 /* SH7751 and SH7751R both have PCI */ 378 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 379 static struct intc_vect vectors_pci[] __initdata = { 380 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 381 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 382 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 383 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 384 }; 385 386 static struct intc_group groups_pci[] __initdata = { 387 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 388 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 389 }; 390 391 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci, 392 mask_registers, prio_registers, NULL); 393 #endif 394 395 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 396 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ 397 defined(CONFIG_CPU_SUBTYPE_SH7091) 398 void __init plat_irq_setup(void) 399 { 400 /* 401 * same vectors for SH7750, SH7750S and SH7091 except for IRLM, 402 * see below.. 403 */ 404 register_intc_controller(&intc_desc); 405 register_intc_controller(&intc_desc_dma4); 406 } 407 #endif 408 409 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) 410 void __init plat_irq_setup(void) 411 { 412 register_intc_controller(&intc_desc); 413 register_intc_controller(&intc_desc_dma8); 414 register_intc_controller(&intc_desc_tmu34); 415 } 416 #endif 417 418 #if defined(CONFIG_CPU_SUBTYPE_SH7751) 419 void __init plat_irq_setup(void) 420 { 421 register_intc_controller(&intc_desc); 422 register_intc_controller(&intc_desc_dma4); 423 register_intc_controller(&intc_desc_tmu34); 424 register_intc_controller(&intc_desc_pci); 425 } 426 #endif 427 428 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) 429 void __init plat_irq_setup(void) 430 { 431 register_intc_controller(&intc_desc); 432 register_intc_controller(&intc_desc_dma8); 433 register_intc_controller(&intc_desc_tmu34); 434 register_intc_controller(&intc_desc_pci); 435 } 436 #endif 437 438 #define INTC_ICR 0xffd00000UL 439 #define INTC_ICR_IRLM (1<<7) 440 441 void __init plat_irq_setup_pins(int mode) 442 { 443 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091) 444 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */ 445 return; 446 #endif 447 448 switch (mode) { 449 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 450 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 451 register_intc_controller(&intc_desc_irlm); 452 break; 453 default: 454 BUG(); 455 } 456 } 457