1 /* 2 * SH4-202 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2009 Magnus Damm 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <linux/io.h> 17 18 static struct plat_sci_port scif0_platform_data = { 19 .mapbase = 0xffe80000, 20 .flags = UPF_BOOT_AUTOCONF, 21 .type = PORT_SCIF, 22 .irqs = { 40, 41, 43, 42 }, 23 }; 24 25 static struct platform_device scif0_device = { 26 .name = "sh-sci", 27 .id = 0, 28 .dev = { 29 .platform_data = &scif0_platform_data, 30 }, 31 }; 32 33 static struct sh_timer_config tmu0_platform_data = { 34 .channel_offset = 0x04, 35 .timer_bit = 0, 36 .clockevent_rating = 200, 37 }; 38 39 static struct resource tmu0_resources[] = { 40 [0] = { 41 .start = 0xffd80008, 42 .end = 0xffd80013, 43 .flags = IORESOURCE_MEM, 44 }, 45 [1] = { 46 .start = 16, 47 .flags = IORESOURCE_IRQ, 48 }, 49 }; 50 51 static struct platform_device tmu0_device = { 52 .name = "sh_tmu", 53 .id = 0, 54 .dev = { 55 .platform_data = &tmu0_platform_data, 56 }, 57 .resource = tmu0_resources, 58 .num_resources = ARRAY_SIZE(tmu0_resources), 59 }; 60 61 static struct sh_timer_config tmu1_platform_data = { 62 .channel_offset = 0x10, 63 .timer_bit = 1, 64 .clocksource_rating = 200, 65 }; 66 67 static struct resource tmu1_resources[] = { 68 [0] = { 69 .start = 0xffd80014, 70 .end = 0xffd8001f, 71 .flags = IORESOURCE_MEM, 72 }, 73 [1] = { 74 .start = 17, 75 .flags = IORESOURCE_IRQ, 76 }, 77 }; 78 79 static struct platform_device tmu1_device = { 80 .name = "sh_tmu", 81 .id = 1, 82 .dev = { 83 .platform_data = &tmu1_platform_data, 84 }, 85 .resource = tmu1_resources, 86 .num_resources = ARRAY_SIZE(tmu1_resources), 87 }; 88 89 static struct sh_timer_config tmu2_platform_data = { 90 .channel_offset = 0x1c, 91 .timer_bit = 2, 92 }; 93 94 static struct resource tmu2_resources[] = { 95 [0] = { 96 .start = 0xffd80020, 97 .end = 0xffd8002f, 98 .flags = IORESOURCE_MEM, 99 }, 100 [1] = { 101 .start = 18, 102 .flags = IORESOURCE_IRQ, 103 }, 104 }; 105 106 static struct platform_device tmu2_device = { 107 .name = "sh_tmu", 108 .id = 2, 109 .dev = { 110 .platform_data = &tmu2_platform_data, 111 }, 112 .resource = tmu2_resources, 113 .num_resources = ARRAY_SIZE(tmu2_resources), 114 }; 115 116 static struct platform_device *sh4202_devices[] __initdata = { 117 &scif0_device, 118 &tmu0_device, 119 &tmu1_device, 120 &tmu2_device, 121 }; 122 123 static int __init sh4202_devices_setup(void) 124 { 125 return platform_add_devices(sh4202_devices, 126 ARRAY_SIZE(sh4202_devices)); 127 } 128 arch_initcall(sh4202_devices_setup); 129 130 static struct platform_device *sh4202_early_devices[] __initdata = { 131 &scif0_device, 132 &tmu0_device, 133 &tmu1_device, 134 &tmu2_device, 135 }; 136 137 void __init plat_early_device_setup(void) 138 { 139 early_platform_add_devices(sh4202_early_devices, 140 ARRAY_SIZE(sh4202_early_devices)); 141 } 142 143 enum { 144 UNUSED = 0, 145 146 /* interrupt sources */ 147 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 148 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, 149 }; 150 151 static struct intc_vect vectors[] __initdata = { 152 INTC_VECT(HUDI, 0x600), 153 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 154 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 155 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 156 INTC_VECT(RTC, 0x4c0), 157 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), 158 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), 159 INTC_VECT(WDT, 0x560), 160 }; 161 162 static struct intc_prio_reg prio_registers[] __initdata = { 163 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 164 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } }, 165 { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } }, 166 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 167 }; 168 169 static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL, 170 NULL, prio_registers, NULL); 171 172 static struct intc_vect vectors_irlm[] __initdata = { 173 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 174 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 175 }; 176 177 static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL, 178 NULL, prio_registers, NULL); 179 180 void __init plat_irq_setup(void) 181 { 182 register_intc_controller(&intc_desc); 183 } 184 185 #define INTC_ICR 0xffd00000UL 186 #define INTC_ICR_IRLM (1<<7) 187 188 void __init plat_irq_setup_pins(int mode) 189 { 190 switch (mode) { 191 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 192 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 193 register_intc_controller(&intc_desc_irlm); 194 break; 195 default: 196 BUG(); 197 } 198 } 199