1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SH4-202 Setup
4  *
5  *  Copyright (C) 2006  Paul Mundt
6  *  Copyright (C) 2009  Magnus Damm
7  */
8 #include <linux/platform_device.h>
9 #include <linux/init.h>
10 #include <linux/serial.h>
11 #include <linux/serial_sci.h>
12 #include <linux/sh_timer.h>
13 #include <linux/sh_intc.h>
14 #include <linux/io.h>
15 #include <asm/platform_early.h>
16 
17 static struct plat_sci_port scif0_platform_data = {
18 	.scscr		= SCSCR_REIE,
19 	.type		= PORT_SCIF,
20 };
21 
22 static struct resource scif0_resources[] = {
23 	DEFINE_RES_MEM(0xffe80000, 0x100),
24 	DEFINE_RES_IRQ(evt2irq(0x700)),
25 	DEFINE_RES_IRQ(evt2irq(0x720)),
26 	DEFINE_RES_IRQ(evt2irq(0x760)),
27 	DEFINE_RES_IRQ(evt2irq(0x740)),
28 };
29 
30 static struct platform_device scif0_device = {
31 	.name		= "sh-sci",
32 	.id		= 0,
33 	.resource	= scif0_resources,
34 	.num_resources	= ARRAY_SIZE(scif0_resources),
35 	.dev		= {
36 		.platform_data	= &scif0_platform_data,
37 	},
38 };
39 
40 static struct sh_timer_config tmu0_platform_data = {
41 	.channels_mask = 7,
42 };
43 
44 static struct resource tmu0_resources[] = {
45 	DEFINE_RES_MEM(0xffd80000, 0x30),
46 	DEFINE_RES_IRQ(evt2irq(0x400)),
47 	DEFINE_RES_IRQ(evt2irq(0x420)),
48 	DEFINE_RES_IRQ(evt2irq(0x440)),
49 };
50 
51 static struct platform_device tmu0_device = {
52 	.name		= "sh-tmu",
53 	.id		= 0,
54 	.dev = {
55 		.platform_data	= &tmu0_platform_data,
56 	},
57 	.resource	= tmu0_resources,
58 	.num_resources	= ARRAY_SIZE(tmu0_resources),
59 };
60 
61 static struct platform_device *sh4202_devices[] __initdata = {
62 	&scif0_device,
63 	&tmu0_device,
64 };
65 
66 static int __init sh4202_devices_setup(void)
67 {
68 	return platform_add_devices(sh4202_devices,
69 				    ARRAY_SIZE(sh4202_devices));
70 }
71 arch_initcall(sh4202_devices_setup);
72 
73 static struct platform_device *sh4202_early_devices[] __initdata = {
74 	&scif0_device,
75 	&tmu0_device,
76 };
77 
78 void __init plat_early_device_setup(void)
79 {
80 	sh_early_platform_add_devices(sh4202_early_devices,
81 				   ARRAY_SIZE(sh4202_early_devices));
82 }
83 
84 enum {
85 	UNUSED = 0,
86 
87 	/* interrupt sources */
88 	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
89 	HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
90 };
91 
92 static struct intc_vect vectors[] __initdata = {
93 	INTC_VECT(HUDI, 0x600),
94 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
95 	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
96 	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
97 	INTC_VECT(RTC, 0x4c0),
98 	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
99 	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
100 	INTC_VECT(WDT, 0x560),
101 };
102 
103 static struct intc_prio_reg prio_registers[] __initdata = {
104 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
105 	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
106 	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
107 	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
108 };
109 
110 static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
111 			 NULL, prio_registers, NULL);
112 
113 static struct intc_vect vectors_irlm[] __initdata = {
114 	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
115 	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
116 };
117 
118 static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
119 			 NULL, prio_registers, NULL);
120 
121 void __init plat_irq_setup(void)
122 {
123 	register_intc_controller(&intc_desc);
124 }
125 
126 #define INTC_ICR	0xffd00000UL
127 #define INTC_ICR_IRLM   (1<<7)
128 
129 void __init plat_irq_setup_pins(int mode)
130 {
131 	switch (mode) {
132 	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
133 		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
134 		register_intc_controller(&intc_desc_irlm);
135 		break;
136 	default:
137 		BUG();
138 	}
139 }
140