1 /* 2 * arch/sh/kernel/cpu/sh4/probe.c 3 * 4 * CPU Subtype Probing for SH-4. 5 * 6 * Copyright (C) 2001 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <asm/processor.h> 16 #include <asm/cache.h> 17 18 int __init detect_cpu_and_cache_system(void) 19 { 20 unsigned long pvr, prr, cvr; 21 unsigned long size; 22 23 static unsigned long sizes[16] = { 24 [1] = (1 << 12), 25 [2] = (1 << 13), 26 [4] = (1 << 14), 27 [8] = (1 << 15), 28 [9] = (1 << 16) 29 }; 30 31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff; 32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff; 33 cvr = (ctrl_inl(CCN_CVR)); 34 35 /* 36 * Setup some sane SH-4 defaults for the icache 37 */ 38 boot_cpu_data.icache.way_incr = (1 << 13); 39 boot_cpu_data.icache.entry_shift = 5; 40 boot_cpu_data.icache.sets = 256; 41 boot_cpu_data.icache.ways = 1; 42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; 43 44 /* 45 * And again for the dcache .. 46 */ 47 boot_cpu_data.dcache.way_incr = (1 << 14); 48 boot_cpu_data.dcache.entry_shift = 5; 49 boot_cpu_data.dcache.sets = 512; 50 boot_cpu_data.dcache.ways = 1; 51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 52 53 /* We don't know the chip cut */ 54 boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1; 55 56 /* 57 * Setup some generic flags we can probe on SH-4A parts 58 */ 59 if (((pvr >> 16) & 0xff) == 0x10) { 60 boot_cpu_data.family = CPU_FAMILY_SH4A; 61 62 if ((cvr & 0x10000000) == 0) { 63 boot_cpu_data.flags |= CPU_HAS_DSP; 64 boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP; 65 } 66 67 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; 68 boot_cpu_data.cut_major = pvr & 0x7f; 69 70 boot_cpu_data.icache.ways = 4; 71 boot_cpu_data.dcache.ways = 4; 72 } else { 73 /* And some SH-4 defaults.. */ 74 boot_cpu_data.flags |= CPU_HAS_PTEA; 75 boot_cpu_data.family = CPU_FAMILY_SH4; 76 } 77 78 /* FPU detection works for everyone */ 79 if ((cvr & 0x20000000)) 80 boot_cpu_data.flags |= CPU_HAS_FPU; 81 82 /* Mask off the upper chip ID */ 83 pvr &= 0xffff; 84 85 /* 86 * Probe the underlying processor version/revision and 87 * adjust cpu_data setup accordingly. 88 */ 89 switch (pvr) { 90 case 0x205: 91 boot_cpu_data.type = CPU_SH7750; 92 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | 93 CPU_HAS_PERF_COUNTER; 94 break; 95 case 0x206: 96 boot_cpu_data.type = CPU_SH7750S; 97 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | 98 CPU_HAS_PERF_COUNTER; 99 break; 100 case 0x1100: 101 boot_cpu_data.type = CPU_SH7751; 102 break; 103 case 0x2001: 104 case 0x2004: 105 boot_cpu_data.type = CPU_SH7770; 106 break; 107 case 0x2006: 108 case 0x200A: 109 if (prr == 0x61) 110 boot_cpu_data.type = CPU_SH7781; 111 else if (prr == 0xa1) 112 boot_cpu_data.type = CPU_SH7763; 113 else 114 boot_cpu_data.type = CPU_SH7780; 115 116 break; 117 case 0x3000: 118 case 0x3003: 119 case 0x3009: 120 boot_cpu_data.type = CPU_SH7343; 121 break; 122 case 0x3004: 123 case 0x3007: 124 boot_cpu_data.type = CPU_SH7785; 125 break; 126 case 0x4004: 127 boot_cpu_data.type = CPU_SH7786; 128 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; 129 break; 130 case 0x3008: 131 switch (prr) { 132 case 0x50: 133 case 0x51: 134 boot_cpu_data.type = CPU_SH7723; 135 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 136 break; 137 case 0x70: 138 boot_cpu_data.type = CPU_SH7366; 139 break; 140 case 0xa0: 141 case 0xa1: 142 boot_cpu_data.type = CPU_SH7722; 143 break; 144 } 145 break; 146 case 0x300b: 147 switch (prr) { 148 case 0x20: 149 boot_cpu_data.type = CPU_SH7724; 150 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 151 break; 152 case 0x50: 153 boot_cpu_data.type = CPU_SH7757; 154 break; 155 } 156 break; 157 case 0x4000: /* 1st cut */ 158 case 0x4001: /* 2nd cut */ 159 boot_cpu_data.type = CPU_SHX3; 160 break; 161 case 0x700: 162 boot_cpu_data.type = CPU_SH4_501; 163 boot_cpu_data.icache.ways = 2; 164 boot_cpu_data.dcache.ways = 2; 165 break; 166 case 0x600: 167 boot_cpu_data.type = CPU_SH4_202; 168 boot_cpu_data.icache.ways = 2; 169 boot_cpu_data.dcache.ways = 2; 170 break; 171 case 0x500 ... 0x501: 172 switch (prr) { 173 case 0x10: 174 boot_cpu_data.type = CPU_SH7750R; 175 break; 176 case 0x11: 177 boot_cpu_data.type = CPU_SH7751R; 178 break; 179 case 0x50 ... 0x5f: 180 boot_cpu_data.type = CPU_SH7760; 181 break; 182 } 183 184 boot_cpu_data.icache.ways = 2; 185 boot_cpu_data.dcache.ways = 2; 186 187 break; 188 } 189 190 /* 191 * On anything that's not a direct-mapped cache, look to the CVR 192 * for I/D-cache specifics. 193 */ 194 if (boot_cpu_data.icache.ways > 1) { 195 size = sizes[(cvr >> 20) & 0xf]; 196 boot_cpu_data.icache.way_incr = (size >> 1); 197 boot_cpu_data.icache.sets = (size >> 6); 198 199 } 200 201 /* And the rest of the D-cache */ 202 if (boot_cpu_data.dcache.ways > 1) { 203 size = sizes[(cvr >> 16) & 0xf]; 204 boot_cpu_data.dcache.way_incr = (size >> 1); 205 boot_cpu_data.dcache.sets = (size >> 6); 206 } 207 208 /* 209 * SH-4A's have an optional PIPT L2. 210 */ 211 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { 212 /* 213 * Verify that it really has something hooked up, this 214 * is the safety net for CPUs that have optional L2 215 * support yet do not implement it. 216 */ 217 if ((cvr & 0xf) == 0) 218 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE; 219 else { 220 /* 221 * Silicon and specifications have clearly never 222 * met.. 223 */ 224 cvr ^= 0xf; 225 226 /* 227 * Size calculation is much more sensible 228 * than it is for the L1. 229 * 230 * Sizes are 128KB, 258KB, 512KB, and 1MB. 231 */ 232 size = (cvr & 0xf) << 17; 233 234 boot_cpu_data.scache.way_incr = (1 << 16); 235 boot_cpu_data.scache.entry_shift = 5; 236 boot_cpu_data.scache.ways = 4; 237 boot_cpu_data.scache.linesz = L1_CACHE_BYTES; 238 239 boot_cpu_data.scache.entry_mask = 240 (boot_cpu_data.scache.way_incr - 241 boot_cpu_data.scache.linesz); 242 243 boot_cpu_data.scache.sets = size / 244 (boot_cpu_data.scache.linesz * 245 boot_cpu_data.scache.ways); 246 247 boot_cpu_data.scache.way_size = 248 (boot_cpu_data.scache.sets * 249 boot_cpu_data.scache.linesz); 250 } 251 } 252 253 return 0; 254 } 255