1 /* 2 * arch/sh/kernel/cpu/sh4/probe.c 3 * 4 * CPU Subtype Probing for SH-4. 5 * 6 * Copyright (C) 2001 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <asm/processor.h> 16 #include <asm/cache.h> 17 18 void __cpuinit cpu_probe(void) 19 { 20 unsigned long pvr, prr, cvr; 21 unsigned long size; 22 23 static unsigned long sizes[16] = { 24 [1] = (1 << 12), 25 [2] = (1 << 13), 26 [4] = (1 << 14), 27 [8] = (1 << 15), 28 [9] = (1 << 16) 29 }; 30 31 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff; 32 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; 33 cvr = (__raw_readl(CCN_CVR)); 34 35 /* 36 * Setup some sane SH-4 defaults for the icache 37 */ 38 boot_cpu_data.icache.way_incr = (1 << 13); 39 boot_cpu_data.icache.entry_shift = 5; 40 boot_cpu_data.icache.sets = 256; 41 boot_cpu_data.icache.ways = 1; 42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; 43 44 /* 45 * And again for the dcache .. 46 */ 47 boot_cpu_data.dcache.way_incr = (1 << 14); 48 boot_cpu_data.dcache.entry_shift = 5; 49 boot_cpu_data.dcache.sets = 512; 50 boot_cpu_data.dcache.ways = 1; 51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 52 53 /* We don't know the chip cut */ 54 boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1; 55 56 /* 57 * Setup some generic flags we can probe on SH-4A parts 58 */ 59 if (((pvr >> 16) & 0xff) == 0x10) { 60 boot_cpu_data.family = CPU_FAMILY_SH4A; 61 62 if ((cvr & 0x10000000) == 0) { 63 boot_cpu_data.flags |= CPU_HAS_DSP; 64 boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP; 65 } 66 67 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; 68 boot_cpu_data.cut_major = pvr & 0x7f; 69 70 boot_cpu_data.icache.ways = 4; 71 boot_cpu_data.dcache.ways = 4; 72 } else { 73 /* And some SH-4 defaults.. */ 74 boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU; 75 boot_cpu_data.family = CPU_FAMILY_SH4; 76 } 77 78 /* FPU detection works for almost everyone */ 79 if ((cvr & 0x20000000)) 80 boot_cpu_data.flags |= CPU_HAS_FPU; 81 82 /* Mask off the upper chip ID */ 83 pvr &= 0xffff; 84 85 /* 86 * Probe the underlying processor version/revision and 87 * adjust cpu_data setup accordingly. 88 */ 89 switch (pvr) { 90 case 0x205: 91 boot_cpu_data.type = CPU_SH7750; 92 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | 93 CPU_HAS_PERF_COUNTER; 94 break; 95 case 0x206: 96 boot_cpu_data.type = CPU_SH7750S; 97 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | 98 CPU_HAS_PERF_COUNTER; 99 break; 100 case 0x1100: 101 boot_cpu_data.type = CPU_SH7751; 102 break; 103 case 0x2001: 104 case 0x2004: 105 boot_cpu_data.type = CPU_SH7770; 106 break; 107 case 0x2006: 108 case 0x200A: 109 if (prr == 0x61) 110 boot_cpu_data.type = CPU_SH7781; 111 else if (prr == 0xa1) 112 boot_cpu_data.type = CPU_SH7763; 113 else 114 boot_cpu_data.type = CPU_SH7780; 115 116 break; 117 case 0x3000: 118 case 0x3003: 119 case 0x3009: 120 boot_cpu_data.type = CPU_SH7343; 121 break; 122 case 0x3004: 123 case 0x3007: 124 boot_cpu_data.type = CPU_SH7785; 125 break; 126 case 0x4004: 127 case 0x4005: 128 boot_cpu_data.type = CPU_SH7786; 129 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; 130 break; 131 case 0x3008: 132 switch (prr) { 133 case 0x50: 134 case 0x51: 135 boot_cpu_data.type = CPU_SH7723; 136 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 137 break; 138 case 0x70: 139 boot_cpu_data.type = CPU_SH7366; 140 break; 141 case 0xa0: 142 case 0xa1: 143 boot_cpu_data.type = CPU_SH7722; 144 break; 145 } 146 break; 147 case 0x300b: 148 switch (prr) { 149 case 0x20: 150 boot_cpu_data.type = CPU_SH7724; 151 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 152 break; 153 case 0x50: 154 boot_cpu_data.type = CPU_SH7757; 155 break; 156 } 157 break; 158 case 0x4000: /* 1st cut */ 159 case 0x4001: /* 2nd cut */ 160 boot_cpu_data.type = CPU_SHX3; 161 break; 162 case 0x700: 163 boot_cpu_data.type = CPU_SH4_501; 164 boot_cpu_data.flags &= ~CPU_HAS_FPU; 165 boot_cpu_data.icache.ways = 2; 166 boot_cpu_data.dcache.ways = 2; 167 break; 168 case 0x600: 169 boot_cpu_data.type = CPU_SH4_202; 170 boot_cpu_data.icache.ways = 2; 171 boot_cpu_data.dcache.ways = 2; 172 break; 173 case 0x500 ... 0x501: 174 switch (prr) { 175 case 0x10: 176 boot_cpu_data.type = CPU_SH7750R; 177 break; 178 case 0x11: 179 boot_cpu_data.type = CPU_SH7751R; 180 break; 181 case 0x50 ... 0x5f: 182 boot_cpu_data.type = CPU_SH7760; 183 break; 184 } 185 186 boot_cpu_data.icache.ways = 2; 187 boot_cpu_data.dcache.ways = 2; 188 189 break; 190 } 191 192 /* 193 * On anything that's not a direct-mapped cache, look to the CVR 194 * for I/D-cache specifics. 195 */ 196 if (boot_cpu_data.icache.ways > 1) { 197 size = sizes[(cvr >> 20) & 0xf]; 198 boot_cpu_data.icache.way_incr = (size >> 1); 199 boot_cpu_data.icache.sets = (size >> 6); 200 201 } 202 203 /* And the rest of the D-cache */ 204 if (boot_cpu_data.dcache.ways > 1) { 205 size = sizes[(cvr >> 16) & 0xf]; 206 boot_cpu_data.dcache.way_incr = (size >> 1); 207 boot_cpu_data.dcache.sets = (size >> 6); 208 } 209 210 /* 211 * SH-4A's have an optional PIPT L2. 212 */ 213 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { 214 /* 215 * Verify that it really has something hooked up, this 216 * is the safety net for CPUs that have optional L2 217 * support yet do not implement it. 218 */ 219 if ((cvr & 0xf) == 0) 220 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE; 221 else { 222 /* 223 * Silicon and specifications have clearly never 224 * met.. 225 */ 226 cvr ^= 0xf; 227 228 /* 229 * Size calculation is much more sensible 230 * than it is for the L1. 231 * 232 * Sizes are 128KB, 256KB, 512KB, and 1MB. 233 */ 234 size = (cvr & 0xf) << 17; 235 236 boot_cpu_data.scache.way_incr = (1 << 16); 237 boot_cpu_data.scache.entry_shift = 5; 238 boot_cpu_data.scache.ways = 4; 239 boot_cpu_data.scache.linesz = L1_CACHE_BYTES; 240 241 boot_cpu_data.scache.entry_mask = 242 (boot_cpu_data.scache.way_incr - 243 boot_cpu_data.scache.linesz); 244 245 boot_cpu_data.scache.sets = size / 246 (boot_cpu_data.scache.linesz * 247 boot_cpu_data.scache.ways); 248 249 boot_cpu_data.scache.way_size = 250 (boot_cpu_data.scache.sets * 251 boot_cpu_data.scache.linesz); 252 } 253 } 254 } 255