1 /* 2 * arch/sh/kernel/cpu/sh4/probe.c 3 * 4 * CPU Subtype Probing for SH-4. 5 * 6 * Copyright (C) 2001 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <asm/processor.h> 16 #include <asm/cache.h> 17 18 int __init detect_cpu_and_cache_system(void) 19 { 20 unsigned long pvr, prr, cvr; 21 unsigned long size; 22 23 static unsigned long sizes[16] = { 24 [1] = (1 << 12), 25 [2] = (1 << 13), 26 [4] = (1 << 14), 27 [8] = (1 << 15), 28 [9] = (1 << 16) 29 }; 30 31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff; 32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff; 33 cvr = (ctrl_inl(CCN_CVR)); 34 35 /* 36 * Setup some sane SH-4 defaults for the icache 37 */ 38 boot_cpu_data.icache.way_incr = (1 << 13); 39 boot_cpu_data.icache.entry_shift = 5; 40 boot_cpu_data.icache.sets = 256; 41 boot_cpu_data.icache.ways = 1; 42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; 43 44 /* 45 * And again for the dcache .. 46 */ 47 boot_cpu_data.dcache.way_incr = (1 << 14); 48 boot_cpu_data.dcache.entry_shift = 5; 49 boot_cpu_data.dcache.sets = 512; 50 boot_cpu_data.dcache.ways = 1; 51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 52 53 /* 54 * Setup some generic flags we can probe on SH-4A parts 55 */ 56 if (((pvr >> 24) & 0xff) == 0x10) { 57 if ((cvr & 0x10000000) == 0) 58 boot_cpu_data.flags |= CPU_HAS_DSP; 59 60 boot_cpu_data.flags |= CPU_HAS_LLSC; 61 } 62 63 /* FPU detection works for everyone */ 64 if ((cvr & 0x20000000) == 1) 65 boot_cpu_data.flags |= CPU_HAS_FPU; 66 67 /* Mask off the upper chip ID */ 68 pvr &= 0xffff; 69 70 /* 71 * Probe the underlying processor version/revision and 72 * adjust cpu_data setup accordingly. 73 */ 74 switch (pvr) { 75 case 0x205: 76 boot_cpu_data.type = CPU_SH7750; 77 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 78 CPU_HAS_PERF_COUNTER; 79 break; 80 case 0x206: 81 boot_cpu_data.type = CPU_SH7750S; 82 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 83 CPU_HAS_PERF_COUNTER; 84 break; 85 case 0x1100: 86 boot_cpu_data.type = CPU_SH7751; 87 boot_cpu_data.flags |= CPU_HAS_FPU; 88 break; 89 case 0x2001: 90 case 0x2004: 91 boot_cpu_data.type = CPU_SH7770; 92 boot_cpu_data.icache.ways = 4; 93 boot_cpu_data.dcache.ways = 4; 94 95 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; 96 break; 97 case 0x2006: 98 case 0x200A: 99 if (prr == 0x61) 100 boot_cpu_data.type = CPU_SH7781; 101 else if (prr == 0xa1) 102 boot_cpu_data.type = CPU_SH7763; 103 else 104 boot_cpu_data.type = CPU_SH7780; 105 106 boot_cpu_data.icache.ways = 4; 107 boot_cpu_data.dcache.ways = 4; 108 109 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 110 CPU_HAS_LLSC; 111 break; 112 case 0x3000: 113 case 0x3003: 114 case 0x3009: 115 boot_cpu_data.type = CPU_SH7343; 116 boot_cpu_data.icache.ways = 4; 117 boot_cpu_data.dcache.ways = 4; 118 boot_cpu_data.flags |= CPU_HAS_LLSC; 119 break; 120 case 0x3004: 121 case 0x3007: 122 boot_cpu_data.type = CPU_SH7785; 123 boot_cpu_data.icache.ways = 4; 124 boot_cpu_data.dcache.ways = 4; 125 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 126 CPU_HAS_LLSC; 127 break; 128 case 0x3008: 129 boot_cpu_data.icache.ways = 4; 130 boot_cpu_data.dcache.ways = 4; 131 boot_cpu_data.flags |= CPU_HAS_LLSC; 132 133 switch (prr) { 134 case 0x50: 135 boot_cpu_data.type = CPU_SH7723; 136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; 137 break; 138 case 0x70: 139 boot_cpu_data.type = CPU_SH7366; 140 break; 141 case 0xa0: 142 case 0xa1: 143 boot_cpu_data.type = CPU_SH7722; 144 break; 145 } 146 break; 147 case 0x4000: /* 1st cut */ 148 case 0x4001: /* 2nd cut */ 149 boot_cpu_data.type = CPU_SHX3; 150 boot_cpu_data.icache.ways = 4; 151 boot_cpu_data.dcache.ways = 4; 152 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 153 CPU_HAS_LLSC; 154 break; 155 case 0x700: 156 boot_cpu_data.type = CPU_SH4_501; 157 boot_cpu_data.icache.ways = 2; 158 boot_cpu_data.dcache.ways = 2; 159 break; 160 case 0x600: 161 boot_cpu_data.type = CPU_SH4_202; 162 boot_cpu_data.icache.ways = 2; 163 boot_cpu_data.dcache.ways = 2; 164 boot_cpu_data.flags |= CPU_HAS_FPU; 165 break; 166 case 0x500 ... 0x501: 167 switch (prr) { 168 case 0x10: 169 boot_cpu_data.type = CPU_SH7750R; 170 break; 171 case 0x11: 172 boot_cpu_data.type = CPU_SH7751R; 173 break; 174 case 0x50 ... 0x5f: 175 boot_cpu_data.type = CPU_SH7760; 176 break; 177 } 178 179 boot_cpu_data.icache.ways = 2; 180 boot_cpu_data.dcache.ways = 2; 181 182 boot_cpu_data.flags |= CPU_HAS_FPU; 183 184 break; 185 default: 186 boot_cpu_data.type = CPU_SH_NONE; 187 break; 188 } 189 190 #ifdef CONFIG_SH_DIRECT_MAPPED 191 boot_cpu_data.icache.ways = 1; 192 boot_cpu_data.dcache.ways = 1; 193 #endif 194 195 #ifdef CONFIG_CPU_HAS_PTEA 196 boot_cpu_data.flags |= CPU_HAS_PTEA; 197 #endif 198 199 /* 200 * On anything that's not a direct-mapped cache, look to the CVR 201 * for I/D-cache specifics. 202 */ 203 if (boot_cpu_data.icache.ways > 1) { 204 size = sizes[(cvr >> 20) & 0xf]; 205 boot_cpu_data.icache.way_incr = (size >> 1); 206 boot_cpu_data.icache.sets = (size >> 6); 207 208 } 209 210 /* And the rest of the D-cache */ 211 if (boot_cpu_data.dcache.ways > 1) { 212 size = sizes[(cvr >> 16) & 0xf]; 213 boot_cpu_data.dcache.way_incr = (size >> 1); 214 boot_cpu_data.dcache.sets = (size >> 6); 215 } 216 217 /* 218 * Setup the L2 cache desc 219 * 220 * SH-4A's have an optional PIPT L2. 221 */ 222 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { 223 /* Bug if we can't decode the L2 info */ 224 BUG_ON(!(cvr & 0xf)); 225 226 /* Silicon and specifications have clearly never met.. */ 227 cvr ^= 0xf; 228 229 /* 230 * Size calculation is much more sensible 231 * than it is for the L1. 232 * 233 * Sizes are 128KB, 258KB, 512KB, and 1MB. 234 */ 235 size = (cvr & 0xf) << 17; 236 237 BUG_ON(!size); 238 239 boot_cpu_data.scache.way_incr = (1 << 16); 240 boot_cpu_data.scache.entry_shift = 5; 241 boot_cpu_data.scache.ways = 4; 242 boot_cpu_data.scache.linesz = L1_CACHE_BYTES; 243 244 boot_cpu_data.scache.entry_mask = 245 (boot_cpu_data.scache.way_incr - 246 boot_cpu_data.scache.linesz); 247 248 boot_cpu_data.scache.sets = size / 249 (boot_cpu_data.scache.linesz * 250 boot_cpu_data.scache.ways); 251 252 boot_cpu_data.scache.way_size = 253 (boot_cpu_data.scache.sets * 254 boot_cpu_data.scache.linesz); 255 } 256 257 return 0; 258 } 259