1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sh/kernel/cpu/sh4/clock-sh4.c 4 * 5 * Generic SH-4 support for the clock framework 6 * 7 * Copyright (C) 2005 Paul Mundt 8 * 9 * FRQCR parsing hacked out of arch/sh/kernel/time.c 10 * 11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 12 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> 13 * Copyright (C) 2002, 2003, 2004 Paul Mundt 14 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org> 15 */ 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <asm/clock.h> 19 #include <asm/freq.h> 20 #include <asm/io.h> 21 22 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 }; 23 #define bfc_divisors ifc_divisors /* Same */ 24 static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 }; 25 26 static void master_clk_init(struct clk *clk) 27 { 28 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; 29 } 30 31 static struct sh_clk_ops sh4_master_clk_ops = { 32 .init = master_clk_init, 33 }; 34 35 static unsigned long module_clk_recalc(struct clk *clk) 36 { 37 int idx = (__raw_readw(FRQCR) & 0x0007); 38 return clk->parent->rate / pfc_divisors[idx]; 39 } 40 41 static struct sh_clk_ops sh4_module_clk_ops = { 42 .recalc = module_clk_recalc, 43 }; 44 45 static unsigned long bus_clk_recalc(struct clk *clk) 46 { 47 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; 48 return clk->parent->rate / bfc_divisors[idx]; 49 } 50 51 static struct sh_clk_ops sh4_bus_clk_ops = { 52 .recalc = bus_clk_recalc, 53 }; 54 55 static unsigned long cpu_clk_recalc(struct clk *clk) 56 { 57 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; 58 return clk->parent->rate / ifc_divisors[idx]; 59 } 60 61 static struct sh_clk_ops sh4_cpu_clk_ops = { 62 .recalc = cpu_clk_recalc, 63 }; 64 65 static struct sh_clk_ops *sh4_clk_ops[] = { 66 &sh4_master_clk_ops, 67 &sh4_module_clk_ops, 68 &sh4_bus_clk_ops, 69 &sh4_cpu_clk_ops, 70 }; 71 72 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) 73 { 74 if (idx < ARRAY_SIZE(sh4_clk_ops)) 75 *ops = sh4_clk_ops[idx]; 76 } 77 78