1 /* 2 * Setup code for SH7720, SH7721. 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * Copyright (C) 2006 Jamie Lenehan 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/platform_device.h> 17 #include <linux/init.h> 18 #include <linux/serial.h> 19 #include <linux/io.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <asm/rtc.h> 23 24 static struct resource rtc_resources[] = { 25 [0] = { 26 .start = 0xa413fec0, 27 .end = 0xa413fec0 + 0x28 - 1, 28 .flags = IORESOURCE_IO, 29 }, 30 [1] = { 31 /* Shared Period/Carry/Alarm IRQ */ 32 .start = 20, 33 .flags = IORESOURCE_IRQ, 34 }, 35 }; 36 37 static struct sh_rtc_platform_info rtc_info = { 38 .capabilities = RTC_CAP_4_DIGIT_YEAR, 39 }; 40 41 static struct platform_device rtc_device = { 42 .name = "sh-rtc", 43 .id = -1, 44 .num_resources = ARRAY_SIZE(rtc_resources), 45 .resource = rtc_resources, 46 .dev = { 47 .platform_data = &rtc_info, 48 }, 49 }; 50 51 static struct plat_sci_port scif0_platform_data = { 52 .mapbase = 0xa4430000, 53 .flags = UPF_BOOT_AUTOCONF, 54 .scscr = SCSCR_RE | SCSCR_TE, 55 .scbrr_algo_id = SCBRR_ALGO_4, 56 .type = PORT_SCIF, 57 .irqs = { 80, 80, 80, 80 }, 58 }; 59 60 static struct platform_device scif0_device = { 61 .name = "sh-sci", 62 .id = 0, 63 .dev = { 64 .platform_data = &scif0_platform_data, 65 }, 66 }; 67 68 static struct plat_sci_port scif1_platform_data = { 69 .mapbase = 0xa4438000, 70 .flags = UPF_BOOT_AUTOCONF, 71 .scscr = SCSCR_RE | SCSCR_TE, 72 .scbrr_algo_id = SCBRR_ALGO_4, 73 .type = PORT_SCIF, 74 .irqs = { 81, 81, 81, 81 }, 75 }; 76 77 static struct platform_device scif1_device = { 78 .name = "sh-sci", 79 .id = 1, 80 .dev = { 81 .platform_data = &scif1_platform_data, 82 }, 83 }; 84 85 static struct resource usb_ohci_resources[] = { 86 [0] = { 87 .start = 0xA4428000, 88 .end = 0xA44280FF, 89 .flags = IORESOURCE_MEM, 90 }, 91 [1] = { 92 .start = 67, 93 .end = 67, 94 .flags = IORESOURCE_IRQ, 95 }, 96 }; 97 98 static u64 usb_ohci_dma_mask = 0xffffffffUL; 99 static struct platform_device usb_ohci_device = { 100 .name = "sh_ohci", 101 .id = -1, 102 .dev = { 103 .dma_mask = &usb_ohci_dma_mask, 104 .coherent_dma_mask = 0xffffffff, 105 }, 106 .num_resources = ARRAY_SIZE(usb_ohci_resources), 107 .resource = usb_ohci_resources, 108 }; 109 110 static struct resource usbf_resources[] = { 111 [0] = { 112 .name = "sh_udc", 113 .start = 0xA4420000, 114 .end = 0xA44200FF, 115 .flags = IORESOURCE_MEM, 116 }, 117 [1] = { 118 .name = "sh_udc", 119 .start = 65, 120 .end = 65, 121 .flags = IORESOURCE_IRQ, 122 }, 123 }; 124 125 static struct platform_device usbf_device = { 126 .name = "sh_udc", 127 .id = -1, 128 .dev = { 129 .dma_mask = NULL, 130 .coherent_dma_mask = 0xffffffff, 131 }, 132 .num_resources = ARRAY_SIZE(usbf_resources), 133 .resource = usbf_resources, 134 }; 135 136 static struct sh_timer_config cmt0_platform_data = { 137 .channel_offset = 0x10, 138 .timer_bit = 0, 139 .clockevent_rating = 125, 140 .clocksource_rating = 125, 141 }; 142 143 static struct resource cmt0_resources[] = { 144 [0] = { 145 .start = 0x044a0010, 146 .end = 0x044a001b, 147 .flags = IORESOURCE_MEM, 148 }, 149 [1] = { 150 .start = 104, 151 .flags = IORESOURCE_IRQ, 152 }, 153 }; 154 155 static struct platform_device cmt0_device = { 156 .name = "sh_cmt", 157 .id = 0, 158 .dev = { 159 .platform_data = &cmt0_platform_data, 160 }, 161 .resource = cmt0_resources, 162 .num_resources = ARRAY_SIZE(cmt0_resources), 163 }; 164 165 static struct sh_timer_config cmt1_platform_data = { 166 .channel_offset = 0x20, 167 .timer_bit = 1, 168 }; 169 170 static struct resource cmt1_resources[] = { 171 [0] = { 172 .start = 0x044a0020, 173 .end = 0x044a002b, 174 .flags = IORESOURCE_MEM, 175 }, 176 [1] = { 177 .start = 104, 178 .flags = IORESOURCE_IRQ, 179 }, 180 }; 181 182 static struct platform_device cmt1_device = { 183 .name = "sh_cmt", 184 .id = 1, 185 .dev = { 186 .platform_data = &cmt1_platform_data, 187 }, 188 .resource = cmt1_resources, 189 .num_resources = ARRAY_SIZE(cmt1_resources), 190 }; 191 192 static struct sh_timer_config cmt2_platform_data = { 193 .channel_offset = 0x30, 194 .timer_bit = 2, 195 }; 196 197 static struct resource cmt2_resources[] = { 198 [0] = { 199 .start = 0x044a0030, 200 .end = 0x044a003b, 201 .flags = IORESOURCE_MEM, 202 }, 203 [1] = { 204 .start = 104, 205 .flags = IORESOURCE_IRQ, 206 }, 207 }; 208 209 static struct platform_device cmt2_device = { 210 .name = "sh_cmt", 211 .id = 2, 212 .dev = { 213 .platform_data = &cmt2_platform_data, 214 }, 215 .resource = cmt2_resources, 216 .num_resources = ARRAY_SIZE(cmt2_resources), 217 }; 218 219 static struct sh_timer_config cmt3_platform_data = { 220 .channel_offset = 0x40, 221 .timer_bit = 3, 222 }; 223 224 static struct resource cmt3_resources[] = { 225 [0] = { 226 .start = 0x044a0040, 227 .end = 0x044a004b, 228 .flags = IORESOURCE_MEM, 229 }, 230 [1] = { 231 .start = 104, 232 .flags = IORESOURCE_IRQ, 233 }, 234 }; 235 236 static struct platform_device cmt3_device = { 237 .name = "sh_cmt", 238 .id = 3, 239 .dev = { 240 .platform_data = &cmt3_platform_data, 241 }, 242 .resource = cmt3_resources, 243 .num_resources = ARRAY_SIZE(cmt3_resources), 244 }; 245 246 static struct sh_timer_config cmt4_platform_data = { 247 .channel_offset = 0x50, 248 .timer_bit = 4, 249 }; 250 251 static struct resource cmt4_resources[] = { 252 [0] = { 253 .start = 0x044a0050, 254 .end = 0x044a005b, 255 .flags = IORESOURCE_MEM, 256 }, 257 [1] = { 258 .start = 104, 259 .flags = IORESOURCE_IRQ, 260 }, 261 }; 262 263 static struct platform_device cmt4_device = { 264 .name = "sh_cmt", 265 .id = 4, 266 .dev = { 267 .platform_data = &cmt4_platform_data, 268 }, 269 .resource = cmt4_resources, 270 .num_resources = ARRAY_SIZE(cmt4_resources), 271 }; 272 273 static struct sh_timer_config tmu0_platform_data = { 274 .channel_offset = 0x02, 275 .timer_bit = 0, 276 .clockevent_rating = 200, 277 }; 278 279 static struct resource tmu0_resources[] = { 280 [0] = { 281 .start = 0xa412fe94, 282 .end = 0xa412fe9f, 283 .flags = IORESOURCE_MEM, 284 }, 285 [1] = { 286 .start = 16, 287 .flags = IORESOURCE_IRQ, 288 }, 289 }; 290 291 static struct platform_device tmu0_device = { 292 .name = "sh_tmu", 293 .id = 0, 294 .dev = { 295 .platform_data = &tmu0_platform_data, 296 }, 297 .resource = tmu0_resources, 298 .num_resources = ARRAY_SIZE(tmu0_resources), 299 }; 300 301 static struct sh_timer_config tmu1_platform_data = { 302 .channel_offset = 0xe, 303 .timer_bit = 1, 304 .clocksource_rating = 200, 305 }; 306 307 static struct resource tmu1_resources[] = { 308 [0] = { 309 .start = 0xa412fea0, 310 .end = 0xa412feab, 311 .flags = IORESOURCE_MEM, 312 }, 313 [1] = { 314 .start = 17, 315 .flags = IORESOURCE_IRQ, 316 }, 317 }; 318 319 static struct platform_device tmu1_device = { 320 .name = "sh_tmu", 321 .id = 1, 322 .dev = { 323 .platform_data = &tmu1_platform_data, 324 }, 325 .resource = tmu1_resources, 326 .num_resources = ARRAY_SIZE(tmu1_resources), 327 }; 328 329 static struct sh_timer_config tmu2_platform_data = { 330 .channel_offset = 0x1a, 331 .timer_bit = 2, 332 }; 333 334 static struct resource tmu2_resources[] = { 335 [0] = { 336 .start = 0xa412feac, 337 .end = 0xa412feb5, 338 .flags = IORESOURCE_MEM, 339 }, 340 [1] = { 341 .start = 18, 342 .flags = IORESOURCE_IRQ, 343 }, 344 }; 345 346 static struct platform_device tmu2_device = { 347 .name = "sh_tmu", 348 .id = 2, 349 .dev = { 350 .platform_data = &tmu2_platform_data, 351 }, 352 .resource = tmu2_resources, 353 .num_resources = ARRAY_SIZE(tmu2_resources), 354 }; 355 356 static struct platform_device *sh7720_devices[] __initdata = { 357 &scif0_device, 358 &scif1_device, 359 &cmt0_device, 360 &cmt1_device, 361 &cmt2_device, 362 &cmt3_device, 363 &cmt4_device, 364 &tmu0_device, 365 &tmu1_device, 366 &tmu2_device, 367 &rtc_device, 368 &usb_ohci_device, 369 &usbf_device, 370 }; 371 372 static int __init sh7720_devices_setup(void) 373 { 374 return platform_add_devices(sh7720_devices, 375 ARRAY_SIZE(sh7720_devices)); 376 } 377 arch_initcall(sh7720_devices_setup); 378 379 static struct platform_device *sh7720_early_devices[] __initdata = { 380 &scif0_device, 381 &scif1_device, 382 &cmt0_device, 383 &cmt1_device, 384 &cmt2_device, 385 &cmt3_device, 386 &cmt4_device, 387 &tmu0_device, 388 &tmu1_device, 389 &tmu2_device, 390 }; 391 392 void __init plat_early_device_setup(void) 393 { 394 early_platform_add_devices(sh7720_early_devices, 395 ARRAY_SIZE(sh7720_early_devices)); 396 } 397 398 enum { 399 UNUSED = 0, 400 401 /* interrupt sources */ 402 TMU0, TMU1, TMU2, RTC, 403 WDT, REF_RCMI, SIM, 404 IRQ0, IRQ1, IRQ2, IRQ3, 405 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 406 DMAC1, LCDC, SSL, 407 ADC, DMAC2, USBFI, CMT, 408 SCIF0, SCIF1, 409 PINT07, PINT815, TPU, IIC, 410 SIOF0, SIOF1, MMC, PCC, 411 USBHI, AFEIF, 412 H_UDI, 413 }; 414 415 static struct intc_vect vectors[] __initdata = { 416 /* IRQ0->5 are handled in setup-sh3.c */ 417 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 418 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 419 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 420 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 421 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 422 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 423 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 424 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 425 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 426 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 427 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 428 INTC_VECT(SSL, 0x980), 429 #endif 430 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 431 INTC_VECT(USBHI, 0xa60), 432 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 433 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 434 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 435 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 436 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 437 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 438 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 439 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 440 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 441 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 442 INTC_VECT(AFEIF, 0xfe0), 443 }; 444 445 static struct intc_prio_reg prio_registers[] __initdata = { 446 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 447 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 448 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 449 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 450 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 451 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 452 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 453 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 454 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 455 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 456 }; 457 458 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 459 NULL, prio_registers, NULL); 460 461 void __init plat_irq_setup(void) 462 { 463 register_intc_controller(&intc_desc); 464 plat_irq_setup_sh3(); 465 } 466