1 /* 2 * Setup code for SH7720, SH7721. 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * Copyright (C) 2006 Jamie Lenehan 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/platform_device.h> 17 #include <linux/init.h> 18 #include <linux/serial.h> 19 #include <linux/io.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <linux/sh_intc.h> 23 #include <linux/usb/ohci_pdriver.h> 24 #include <asm/rtc.h> 25 #include <cpu/serial.h> 26 27 static struct resource rtc_resources[] = { 28 [0] = { 29 .start = 0xa413fec0, 30 .end = 0xa413fec0 + 0x28 - 1, 31 .flags = IORESOURCE_IO, 32 }, 33 [1] = { 34 /* Shared Period/Carry/Alarm IRQ */ 35 .start = evt2irq(0x480), 36 .flags = IORESOURCE_IRQ, 37 }, 38 }; 39 40 static struct sh_rtc_platform_info rtc_info = { 41 .capabilities = RTC_CAP_4_DIGIT_YEAR, 42 }; 43 44 static struct platform_device rtc_device = { 45 .name = "sh-rtc", 46 .id = -1, 47 .num_resources = ARRAY_SIZE(rtc_resources), 48 .resource = rtc_resources, 49 .dev = { 50 .platform_data = &rtc_info, 51 }, 52 }; 53 54 static struct plat_sci_port scif0_platform_data = { 55 .flags = UPF_BOOT_AUTOCONF, 56 .scscr = SCSCR_RE | SCSCR_TE, 57 .type = PORT_SCIF, 58 .ops = &sh7720_sci_port_ops, 59 .regtype = SCIx_SH7705_SCIF_REGTYPE, 60 }; 61 62 static struct resource scif0_resources[] = { 63 DEFINE_RES_MEM(0xa4430000, 0x100), 64 DEFINE_RES_IRQ(evt2irq(0xc00)), 65 }; 66 67 static struct platform_device scif0_device = { 68 .name = "sh-sci", 69 .id = 0, 70 .resource = scif0_resources, 71 .num_resources = ARRAY_SIZE(scif0_resources), 72 .dev = { 73 .platform_data = &scif0_platform_data, 74 }, 75 }; 76 77 static struct plat_sci_port scif1_platform_data = { 78 .flags = UPF_BOOT_AUTOCONF, 79 .scscr = SCSCR_RE | SCSCR_TE, 80 .type = PORT_SCIF, 81 .ops = &sh7720_sci_port_ops, 82 .regtype = SCIx_SH7705_SCIF_REGTYPE, 83 }; 84 85 static struct resource scif1_resources[] = { 86 DEFINE_RES_MEM(0xa4438000, 0x100), 87 DEFINE_RES_IRQ(evt2irq(0xc20)), 88 }; 89 90 static struct platform_device scif1_device = { 91 .name = "sh-sci", 92 .id = 1, 93 .resource = scif1_resources, 94 .num_resources = ARRAY_SIZE(scif1_resources), 95 .dev = { 96 .platform_data = &scif1_platform_data, 97 }, 98 }; 99 100 static struct resource usb_ohci_resources[] = { 101 [0] = { 102 .start = 0xA4428000, 103 .end = 0xA44280FF, 104 .flags = IORESOURCE_MEM, 105 }, 106 [1] = { 107 .start = evt2irq(0xa60), 108 .end = evt2irq(0xa60), 109 .flags = IORESOURCE_IRQ, 110 }, 111 }; 112 113 static u64 usb_ohci_dma_mask = 0xffffffffUL; 114 115 static struct usb_ohci_pdata usb_ohci_pdata; 116 117 static struct platform_device usb_ohci_device = { 118 .name = "ohci-platform", 119 .id = -1, 120 .dev = { 121 .dma_mask = &usb_ohci_dma_mask, 122 .coherent_dma_mask = 0xffffffff, 123 .platform_data = &usb_ohci_pdata, 124 }, 125 .num_resources = ARRAY_SIZE(usb_ohci_resources), 126 .resource = usb_ohci_resources, 127 }; 128 129 static struct resource usbf_resources[] = { 130 [0] = { 131 .name = "sh_udc", 132 .start = 0xA4420000, 133 .end = 0xA44200FF, 134 .flags = IORESOURCE_MEM, 135 }, 136 [1] = { 137 .name = "sh_udc", 138 .start = evt2irq(0xa20), 139 .end = evt2irq(0xa20), 140 .flags = IORESOURCE_IRQ, 141 }, 142 }; 143 144 static struct platform_device usbf_device = { 145 .name = "sh_udc", 146 .id = -1, 147 .dev = { 148 .dma_mask = NULL, 149 .coherent_dma_mask = 0xffffffff, 150 }, 151 .num_resources = ARRAY_SIZE(usbf_resources), 152 .resource = usbf_resources, 153 }; 154 155 static struct sh_timer_config cmt_platform_data = { 156 .channels_mask = 0x1f, 157 }; 158 159 static struct resource cmt_resources[] = { 160 DEFINE_RES_MEM(0x044a0000, 0x60), 161 DEFINE_RES_IRQ(evt2irq(0xf00)), 162 }; 163 164 static struct platform_device cmt_device = { 165 .name = "sh-cmt-32", 166 .id = 0, 167 .dev = { 168 .platform_data = &cmt_platform_data, 169 }, 170 .resource = cmt_resources, 171 .num_resources = ARRAY_SIZE(cmt_resources), 172 }; 173 174 static struct sh_timer_config tmu0_platform_data = { 175 .channels_mask = 7, 176 }; 177 178 static struct resource tmu0_resources[] = { 179 DEFINE_RES_MEM(0xa412fe90, 0x28), 180 DEFINE_RES_IRQ(evt2irq(0x400)), 181 DEFINE_RES_IRQ(evt2irq(0x420)), 182 DEFINE_RES_IRQ(evt2irq(0x440)), 183 }; 184 185 static struct platform_device tmu0_device = { 186 .name = "sh-tmu-sh3", 187 .id = 0, 188 .dev = { 189 .platform_data = &tmu0_platform_data, 190 }, 191 .resource = tmu0_resources, 192 .num_resources = ARRAY_SIZE(tmu0_resources), 193 }; 194 195 static struct platform_device *sh7720_devices[] __initdata = { 196 &scif0_device, 197 &scif1_device, 198 &cmt_device, 199 &tmu0_device, 200 &rtc_device, 201 &usb_ohci_device, 202 &usbf_device, 203 }; 204 205 static int __init sh7720_devices_setup(void) 206 { 207 return platform_add_devices(sh7720_devices, 208 ARRAY_SIZE(sh7720_devices)); 209 } 210 arch_initcall(sh7720_devices_setup); 211 212 static struct platform_device *sh7720_early_devices[] __initdata = { 213 &scif0_device, 214 &scif1_device, 215 &cmt_device, 216 &tmu0_device, 217 }; 218 219 void __init plat_early_device_setup(void) 220 { 221 early_platform_add_devices(sh7720_early_devices, 222 ARRAY_SIZE(sh7720_early_devices)); 223 } 224 225 enum { 226 UNUSED = 0, 227 228 /* interrupt sources */ 229 TMU0, TMU1, TMU2, RTC, 230 WDT, REF_RCMI, SIM, 231 IRQ0, IRQ1, IRQ2, IRQ3, 232 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 233 DMAC1, LCDC, SSL, 234 ADC, DMAC2, USBFI, CMT, 235 SCIF0, SCIF1, 236 PINT07, PINT815, TPU, IIC, 237 SIOF0, SIOF1, MMC, PCC, 238 USBHI, AFEIF, 239 H_UDI, 240 }; 241 242 static struct intc_vect vectors[] __initdata = { 243 /* IRQ0->5 are handled in setup-sh3.c */ 244 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 245 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 246 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 247 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 248 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 249 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 250 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 251 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 252 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 253 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 254 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 255 INTC_VECT(SSL, 0x980), 256 #endif 257 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 258 INTC_VECT(USBHI, 0xa60), 259 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 260 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 261 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 262 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 263 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 264 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 265 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 266 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 267 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 268 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 269 INTC_VECT(AFEIF, 0xfe0), 270 }; 271 272 static struct intc_prio_reg prio_registers[] __initdata = { 273 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 274 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 275 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 276 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 277 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 278 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 279 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 280 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 281 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 282 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 283 }; 284 285 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 286 NULL, prio_registers, NULL); 287 288 void __init plat_irq_setup(void) 289 { 290 register_intc_controller(&intc_desc); 291 plat_irq_setup_sh3(); 292 } 293