1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Setup code for SH7720, SH7721. 4 * 5 * Copyright (C) 2007 Markus Brunner, Mark Jonas 6 * Copyright (C) 2009 Paul Mundt 7 * 8 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 9 * 10 * Copyright (C) 2006 Paul Mundt 11 * Copyright (C) 2006 Jamie Lenehan 12 */ 13 #include <linux/platform_device.h> 14 #include <linux/init.h> 15 #include <linux/serial.h> 16 #include <linux/io.h> 17 #include <linux/serial_sci.h> 18 #include <linux/sh_timer.h> 19 #include <linux/sh_intc.h> 20 #include <linux/usb/ohci_pdriver.h> 21 #include <asm/rtc.h> 22 #include <asm/platform_early.h> 23 #include <cpu/serial.h> 24 25 static struct resource rtc_resources[] = { 26 [0] = { 27 .start = 0xa413fec0, 28 .end = 0xa413fec0 + 0x28 - 1, 29 .flags = IORESOURCE_IO, 30 }, 31 [1] = { 32 /* Shared Period/Carry/Alarm IRQ */ 33 .start = evt2irq(0x480), 34 .flags = IORESOURCE_IRQ, 35 }, 36 }; 37 38 static struct sh_rtc_platform_info rtc_info = { 39 .capabilities = RTC_CAP_4_DIGIT_YEAR, 40 }; 41 42 static struct platform_device rtc_device = { 43 .name = "sh-rtc", 44 .id = -1, 45 .num_resources = ARRAY_SIZE(rtc_resources), 46 .resource = rtc_resources, 47 .dev = { 48 .platform_data = &rtc_info, 49 }, 50 }; 51 52 static struct plat_sci_port scif0_platform_data = { 53 .type = PORT_SCIF, 54 .ops = &sh7720_sci_port_ops, 55 .regtype = SCIx_SH7705_SCIF_REGTYPE, 56 }; 57 58 static struct resource scif0_resources[] = { 59 DEFINE_RES_MEM(0xa4430000, 0x100), 60 DEFINE_RES_IRQ(evt2irq(0xc00)), 61 }; 62 63 static struct platform_device scif0_device = { 64 .name = "sh-sci", 65 .id = 0, 66 .resource = scif0_resources, 67 .num_resources = ARRAY_SIZE(scif0_resources), 68 .dev = { 69 .platform_data = &scif0_platform_data, 70 }, 71 }; 72 73 static struct plat_sci_port scif1_platform_data = { 74 .type = PORT_SCIF, 75 .ops = &sh7720_sci_port_ops, 76 .regtype = SCIx_SH7705_SCIF_REGTYPE, 77 }; 78 79 static struct resource scif1_resources[] = { 80 DEFINE_RES_MEM(0xa4438000, 0x100), 81 DEFINE_RES_IRQ(evt2irq(0xc20)), 82 }; 83 84 static struct platform_device scif1_device = { 85 .name = "sh-sci", 86 .id = 1, 87 .resource = scif1_resources, 88 .num_resources = ARRAY_SIZE(scif1_resources), 89 .dev = { 90 .platform_data = &scif1_platform_data, 91 }, 92 }; 93 94 static struct resource usb_ohci_resources[] = { 95 [0] = { 96 .start = 0xA4428000, 97 .end = 0xA44280FF, 98 .flags = IORESOURCE_MEM, 99 }, 100 [1] = { 101 .start = evt2irq(0xa60), 102 .end = evt2irq(0xa60), 103 .flags = IORESOURCE_IRQ, 104 }, 105 }; 106 107 static u64 usb_ohci_dma_mask = 0xffffffffUL; 108 109 static struct usb_ohci_pdata usb_ohci_pdata; 110 111 static struct platform_device usb_ohci_device = { 112 .name = "ohci-platform", 113 .id = -1, 114 .dev = { 115 .dma_mask = &usb_ohci_dma_mask, 116 .coherent_dma_mask = 0xffffffff, 117 .platform_data = &usb_ohci_pdata, 118 }, 119 .num_resources = ARRAY_SIZE(usb_ohci_resources), 120 .resource = usb_ohci_resources, 121 }; 122 123 static struct resource usbf_resources[] = { 124 [0] = { 125 .name = "sh_udc", 126 .start = 0xA4420000, 127 .end = 0xA44200FF, 128 .flags = IORESOURCE_MEM, 129 }, 130 [1] = { 131 .name = "sh_udc", 132 .start = evt2irq(0xa20), 133 .end = evt2irq(0xa20), 134 .flags = IORESOURCE_IRQ, 135 }, 136 }; 137 138 static struct platform_device usbf_device = { 139 .name = "sh_udc", 140 .id = -1, 141 .dev = { 142 .dma_mask = NULL, 143 .coherent_dma_mask = 0xffffffff, 144 }, 145 .num_resources = ARRAY_SIZE(usbf_resources), 146 .resource = usbf_resources, 147 }; 148 149 static struct sh_timer_config cmt_platform_data = { 150 .channels_mask = 0x1f, 151 }; 152 153 static struct resource cmt_resources[] = { 154 DEFINE_RES_MEM(0x044a0000, 0x60), 155 DEFINE_RES_IRQ(evt2irq(0xf00)), 156 }; 157 158 static struct platform_device cmt_device = { 159 .name = "sh-cmt-32", 160 .id = 0, 161 .dev = { 162 .platform_data = &cmt_platform_data, 163 }, 164 .resource = cmt_resources, 165 .num_resources = ARRAY_SIZE(cmt_resources), 166 }; 167 168 static struct sh_timer_config tmu0_platform_data = { 169 .channels_mask = 7, 170 }; 171 172 static struct resource tmu0_resources[] = { 173 DEFINE_RES_MEM(0xa412fe90, 0x28), 174 DEFINE_RES_IRQ(evt2irq(0x400)), 175 DEFINE_RES_IRQ(evt2irq(0x420)), 176 DEFINE_RES_IRQ(evt2irq(0x440)), 177 }; 178 179 static struct platform_device tmu0_device = { 180 .name = "sh-tmu-sh3", 181 .id = 0, 182 .dev = { 183 .platform_data = &tmu0_platform_data, 184 }, 185 .resource = tmu0_resources, 186 .num_resources = ARRAY_SIZE(tmu0_resources), 187 }; 188 189 static struct platform_device *sh7720_devices[] __initdata = { 190 &scif0_device, 191 &scif1_device, 192 &cmt_device, 193 &tmu0_device, 194 &rtc_device, 195 &usb_ohci_device, 196 &usbf_device, 197 }; 198 199 static int __init sh7720_devices_setup(void) 200 { 201 return platform_add_devices(sh7720_devices, 202 ARRAY_SIZE(sh7720_devices)); 203 } 204 arch_initcall(sh7720_devices_setup); 205 206 static struct platform_device *sh7720_early_devices[] __initdata = { 207 &scif0_device, 208 &scif1_device, 209 &cmt_device, 210 &tmu0_device, 211 }; 212 213 void __init plat_early_device_setup(void) 214 { 215 sh_early_platform_add_devices(sh7720_early_devices, 216 ARRAY_SIZE(sh7720_early_devices)); 217 } 218 219 enum { 220 UNUSED = 0, 221 222 /* interrupt sources */ 223 TMU0, TMU1, TMU2, RTC, 224 WDT, REF_RCMI, SIM, 225 IRQ0, IRQ1, IRQ2, IRQ3, 226 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 227 DMAC1, LCDC, SSL, 228 ADC, DMAC2, USBFI, CMT, 229 SCIF0, SCIF1, 230 PINT07, PINT815, TPU, IIC, 231 SIOF0, SIOF1, MMC, PCC, 232 USBHI, AFEIF, 233 H_UDI, 234 }; 235 236 static struct intc_vect vectors[] __initdata = { 237 /* IRQ0->5 are handled in setup-sh3.c */ 238 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 239 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 240 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 241 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 242 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 243 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 244 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 245 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 246 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 247 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 248 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 249 INTC_VECT(SSL, 0x980), 250 #endif 251 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 252 INTC_VECT(USBHI, 0xa60), 253 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 254 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 255 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 256 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 257 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 258 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 259 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 260 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 261 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 262 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 263 INTC_VECT(AFEIF, 0xfe0), 264 }; 265 266 static struct intc_prio_reg prio_registers[] __initdata = { 267 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 268 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 269 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 270 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 271 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 272 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 273 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 274 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 275 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 276 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 277 }; 278 279 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 280 NULL, prio_registers, NULL); 281 282 void __init plat_irq_setup(void) 283 { 284 register_intc_controller(&intc_desc); 285 plat_irq_setup_sh3(); 286 } 287