1 /* 2 * Setup code for SH7720, SH7721. 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * Copyright (C) 2006 Jamie Lenehan 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file "COPYING" in the main directory of this archive 14 * for more details. 15 */ 16 #include <linux/platform_device.h> 17 #include <linux/init.h> 18 #include <linux/serial.h> 19 #include <linux/io.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <linux/sh_intc.h> 23 #include <linux/usb/ohci_pdriver.h> 24 #include <asm/rtc.h> 25 #include <cpu/serial.h> 26 27 static struct resource rtc_resources[] = { 28 [0] = { 29 .start = 0xa413fec0, 30 .end = 0xa413fec0 + 0x28 - 1, 31 .flags = IORESOURCE_IO, 32 }, 33 [1] = { 34 /* Shared Period/Carry/Alarm IRQ */ 35 .start = evt2irq(0x480), 36 .flags = IORESOURCE_IRQ, 37 }, 38 }; 39 40 static struct sh_rtc_platform_info rtc_info = { 41 .capabilities = RTC_CAP_4_DIGIT_YEAR, 42 }; 43 44 static struct platform_device rtc_device = { 45 .name = "sh-rtc", 46 .id = -1, 47 .num_resources = ARRAY_SIZE(rtc_resources), 48 .resource = rtc_resources, 49 .dev = { 50 .platform_data = &rtc_info, 51 }, 52 }; 53 54 static struct plat_sci_port scif0_platform_data = { 55 .mapbase = 0xa4430000, 56 .flags = UPF_BOOT_AUTOCONF, 57 .scscr = SCSCR_RE | SCSCR_TE, 58 .scbrr_algo_id = SCBRR_ALGO_4, 59 .type = PORT_SCIF, 60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 61 .ops = &sh7720_sci_port_ops, 62 .regtype = SCIx_SH7705_SCIF_REGTYPE, 63 }; 64 65 static struct platform_device scif0_device = { 66 .name = "sh-sci", 67 .id = 0, 68 .dev = { 69 .platform_data = &scif0_platform_data, 70 }, 71 }; 72 73 static struct plat_sci_port scif1_platform_data = { 74 .mapbase = 0xa4438000, 75 .flags = UPF_BOOT_AUTOCONF, 76 .scscr = SCSCR_RE | SCSCR_TE, 77 .scbrr_algo_id = SCBRR_ALGO_4, 78 .type = PORT_SCIF, 79 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 80 .ops = &sh7720_sci_port_ops, 81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 82 }; 83 84 static struct platform_device scif1_device = { 85 .name = "sh-sci", 86 .id = 1, 87 .dev = { 88 .platform_data = &scif1_platform_data, 89 }, 90 }; 91 92 static struct resource usb_ohci_resources[] = { 93 [0] = { 94 .start = 0xA4428000, 95 .end = 0xA44280FF, 96 .flags = IORESOURCE_MEM, 97 }, 98 [1] = { 99 .start = evt2irq(0xa60), 100 .end = evt2irq(0xa60), 101 .flags = IORESOURCE_IRQ, 102 }, 103 }; 104 105 static u64 usb_ohci_dma_mask = 0xffffffffUL; 106 107 static struct usb_ohci_pdata usb_ohci_pdata; 108 109 static struct platform_device usb_ohci_device = { 110 .name = "ohci-platform", 111 .id = -1, 112 .dev = { 113 .dma_mask = &usb_ohci_dma_mask, 114 .coherent_dma_mask = 0xffffffff, 115 .platform_data = &usb_ohci_pdata, 116 }, 117 .num_resources = ARRAY_SIZE(usb_ohci_resources), 118 .resource = usb_ohci_resources, 119 }; 120 121 static struct resource usbf_resources[] = { 122 [0] = { 123 .name = "sh_udc", 124 .start = 0xA4420000, 125 .end = 0xA44200FF, 126 .flags = IORESOURCE_MEM, 127 }, 128 [1] = { 129 .name = "sh_udc", 130 .start = evt2irq(0xa20), 131 .end = evt2irq(0xa20), 132 .flags = IORESOURCE_IRQ, 133 }, 134 }; 135 136 static struct platform_device usbf_device = { 137 .name = "sh_udc", 138 .id = -1, 139 .dev = { 140 .dma_mask = NULL, 141 .coherent_dma_mask = 0xffffffff, 142 }, 143 .num_resources = ARRAY_SIZE(usbf_resources), 144 .resource = usbf_resources, 145 }; 146 147 static struct sh_timer_config cmt0_platform_data = { 148 .channel_offset = 0x10, 149 .timer_bit = 0, 150 .clockevent_rating = 125, 151 .clocksource_rating = 125, 152 }; 153 154 static struct resource cmt0_resources[] = { 155 [0] = { 156 .start = 0x044a0010, 157 .end = 0x044a001b, 158 .flags = IORESOURCE_MEM, 159 }, 160 [1] = { 161 .start = evt2irq(0xf00), 162 .flags = IORESOURCE_IRQ, 163 }, 164 }; 165 166 static struct platform_device cmt0_device = { 167 .name = "sh_cmt", 168 .id = 0, 169 .dev = { 170 .platform_data = &cmt0_platform_data, 171 }, 172 .resource = cmt0_resources, 173 .num_resources = ARRAY_SIZE(cmt0_resources), 174 }; 175 176 static struct sh_timer_config cmt1_platform_data = { 177 .channel_offset = 0x20, 178 .timer_bit = 1, 179 }; 180 181 static struct resource cmt1_resources[] = { 182 [0] = { 183 .start = 0x044a0020, 184 .end = 0x044a002b, 185 .flags = IORESOURCE_MEM, 186 }, 187 [1] = { 188 .start = evt2irq(0xf00), 189 .flags = IORESOURCE_IRQ, 190 }, 191 }; 192 193 static struct platform_device cmt1_device = { 194 .name = "sh_cmt", 195 .id = 1, 196 .dev = { 197 .platform_data = &cmt1_platform_data, 198 }, 199 .resource = cmt1_resources, 200 .num_resources = ARRAY_SIZE(cmt1_resources), 201 }; 202 203 static struct sh_timer_config cmt2_platform_data = { 204 .channel_offset = 0x30, 205 .timer_bit = 2, 206 }; 207 208 static struct resource cmt2_resources[] = { 209 [0] = { 210 .start = 0x044a0030, 211 .end = 0x044a003b, 212 .flags = IORESOURCE_MEM, 213 }, 214 [1] = { 215 .start = evt2irq(0xf00), 216 .flags = IORESOURCE_IRQ, 217 }, 218 }; 219 220 static struct platform_device cmt2_device = { 221 .name = "sh_cmt", 222 .id = 2, 223 .dev = { 224 .platform_data = &cmt2_platform_data, 225 }, 226 .resource = cmt2_resources, 227 .num_resources = ARRAY_SIZE(cmt2_resources), 228 }; 229 230 static struct sh_timer_config cmt3_platform_data = { 231 .channel_offset = 0x40, 232 .timer_bit = 3, 233 }; 234 235 static struct resource cmt3_resources[] = { 236 [0] = { 237 .start = 0x044a0040, 238 .end = 0x044a004b, 239 .flags = IORESOURCE_MEM, 240 }, 241 [1] = { 242 .start = evt2irq(0xf00), 243 .flags = IORESOURCE_IRQ, 244 }, 245 }; 246 247 static struct platform_device cmt3_device = { 248 .name = "sh_cmt", 249 .id = 3, 250 .dev = { 251 .platform_data = &cmt3_platform_data, 252 }, 253 .resource = cmt3_resources, 254 .num_resources = ARRAY_SIZE(cmt3_resources), 255 }; 256 257 static struct sh_timer_config cmt4_platform_data = { 258 .channel_offset = 0x50, 259 .timer_bit = 4, 260 }; 261 262 static struct resource cmt4_resources[] = { 263 [0] = { 264 .start = 0x044a0050, 265 .end = 0x044a005b, 266 .flags = IORESOURCE_MEM, 267 }, 268 [1] = { 269 .start = evt2irq(0xf00), 270 .flags = IORESOURCE_IRQ, 271 }, 272 }; 273 274 static struct platform_device cmt4_device = { 275 .name = "sh_cmt", 276 .id = 4, 277 .dev = { 278 .platform_data = &cmt4_platform_data, 279 }, 280 .resource = cmt4_resources, 281 .num_resources = ARRAY_SIZE(cmt4_resources), 282 }; 283 284 static struct sh_timer_config tmu0_platform_data = { 285 .channel_offset = 0x02, 286 .timer_bit = 0, 287 .clockevent_rating = 200, 288 }; 289 290 static struct resource tmu0_resources[] = { 291 [0] = { 292 .start = 0xa412fe94, 293 .end = 0xa412fe9f, 294 .flags = IORESOURCE_MEM, 295 }, 296 [1] = { 297 .start = evt2irq(0x400), 298 .flags = IORESOURCE_IRQ, 299 }, 300 }; 301 302 static struct platform_device tmu0_device = { 303 .name = "sh_tmu", 304 .id = 0, 305 .dev = { 306 .platform_data = &tmu0_platform_data, 307 }, 308 .resource = tmu0_resources, 309 .num_resources = ARRAY_SIZE(tmu0_resources), 310 }; 311 312 static struct sh_timer_config tmu1_platform_data = { 313 .channel_offset = 0xe, 314 .timer_bit = 1, 315 .clocksource_rating = 200, 316 }; 317 318 static struct resource tmu1_resources[] = { 319 [0] = { 320 .start = 0xa412fea0, 321 .end = 0xa412feab, 322 .flags = IORESOURCE_MEM, 323 }, 324 [1] = { 325 .start = evt2irq(0x420), 326 .flags = IORESOURCE_IRQ, 327 }, 328 }; 329 330 static struct platform_device tmu1_device = { 331 .name = "sh_tmu", 332 .id = 1, 333 .dev = { 334 .platform_data = &tmu1_platform_data, 335 }, 336 .resource = tmu1_resources, 337 .num_resources = ARRAY_SIZE(tmu1_resources), 338 }; 339 340 static struct sh_timer_config tmu2_platform_data = { 341 .channel_offset = 0x1a, 342 .timer_bit = 2, 343 }; 344 345 static struct resource tmu2_resources[] = { 346 [0] = { 347 .start = 0xa412feac, 348 .end = 0xa412feb5, 349 .flags = IORESOURCE_MEM, 350 }, 351 [1] = { 352 .start = evt2irq(0x440), 353 .flags = IORESOURCE_IRQ, 354 }, 355 }; 356 357 static struct platform_device tmu2_device = { 358 .name = "sh_tmu", 359 .id = 2, 360 .dev = { 361 .platform_data = &tmu2_platform_data, 362 }, 363 .resource = tmu2_resources, 364 .num_resources = ARRAY_SIZE(tmu2_resources), 365 }; 366 367 static struct platform_device *sh7720_devices[] __initdata = { 368 &scif0_device, 369 &scif1_device, 370 &cmt0_device, 371 &cmt1_device, 372 &cmt2_device, 373 &cmt3_device, 374 &cmt4_device, 375 &tmu0_device, 376 &tmu1_device, 377 &tmu2_device, 378 &rtc_device, 379 &usb_ohci_device, 380 &usbf_device, 381 }; 382 383 static int __init sh7720_devices_setup(void) 384 { 385 return platform_add_devices(sh7720_devices, 386 ARRAY_SIZE(sh7720_devices)); 387 } 388 arch_initcall(sh7720_devices_setup); 389 390 static struct platform_device *sh7720_early_devices[] __initdata = { 391 &scif0_device, 392 &scif1_device, 393 &cmt0_device, 394 &cmt1_device, 395 &cmt2_device, 396 &cmt3_device, 397 &cmt4_device, 398 &tmu0_device, 399 &tmu1_device, 400 &tmu2_device, 401 }; 402 403 void __init plat_early_device_setup(void) 404 { 405 early_platform_add_devices(sh7720_early_devices, 406 ARRAY_SIZE(sh7720_early_devices)); 407 } 408 409 enum { 410 UNUSED = 0, 411 412 /* interrupt sources */ 413 TMU0, TMU1, TMU2, RTC, 414 WDT, REF_RCMI, SIM, 415 IRQ0, IRQ1, IRQ2, IRQ3, 416 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 417 DMAC1, LCDC, SSL, 418 ADC, DMAC2, USBFI, CMT, 419 SCIF0, SCIF1, 420 PINT07, PINT815, TPU, IIC, 421 SIOF0, SIOF1, MMC, PCC, 422 USBHI, AFEIF, 423 H_UDI, 424 }; 425 426 static struct intc_vect vectors[] __initdata = { 427 /* IRQ0->5 are handled in setup-sh3.c */ 428 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 429 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480), 430 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0), 431 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500), 432 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540), 433 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 434 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 435 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800), 436 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840), 437 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900), 438 #if defined(CONFIG_CPU_SUBTYPE_SH7720) 439 INTC_VECT(SSL, 0x980), 440 #endif 441 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40), 442 INTC_VECT(USBHI, 0xa60), 443 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 444 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 445 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 446 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 447 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80), 448 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0), 449 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00), 450 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0), 451 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0), 452 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 453 INTC_VECT(AFEIF, 0xfe0), 454 }; 455 456 static struct intc_prio_reg prio_registers[] __initdata = { 457 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 458 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 459 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 460 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 461 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 462 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 463 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 464 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 465 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 466 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 467 }; 468 469 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL, 470 NULL, prio_registers, NULL); 471 472 void __init plat_irq_setup(void) 473 { 474 register_intc_controller(&intc_desc); 475 plat_irq_setup_sh3(); 476 } 477