1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006, 2007 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <asm/rtc.h> 17 18 enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 26 DMAC_DEI4, DMAC_DEI5, 27 IPSEC, 28 EDMAC0, EDMAC1, EDMAC2, 29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI, 30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI, 31 TMU0, TMU1, TMU2, 32 RTC_ATI, RTC_PRI, RTC_CUI, 33 WDT, 34 REF, 35 36 /* interrupt groups */ 37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, 38 }; 39 40 static struct intc_vect vectors[] __initdata = { 41 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920), 47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960), 48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0), 49 #ifdef CONFIG_CPU_SUBTYPE_SH7710 50 INTC_VECT(IPSEC, 0xbe0), 51 #endif 52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 53 INTC_VECT(EDMAC2, 0xc40), 54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20), 55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60), 56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0), 57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0), 58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 59 INTC_VECT(TMU2, 0x440), 60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 61 INTC_VECT(RTC_CUI, 0x4c0), 62 INTC_VECT(WDT, 0x560), 63 INTC_VECT(REF, 0x580), 64 }; 65 66 static struct intc_group groups[] __initdata = { 67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), 69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5), 72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI), 73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI), 74 }; 75 76 static struct intc_prio_reg prio_registers[] __initdata = { 77 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 78 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 79 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 80 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 81 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 82 { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } }, 83 #ifdef CONFIG_CPU_SUBTYPE_SH7710 84 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } }, 85 #endif 86 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 87 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 88 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 89 }; 90 91 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 92 NULL, prio_registers, NULL); 93 94 static struct intc_vect vectors_irq[] __initdata = { 95 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 96 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 97 }; 98 99 static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL, 100 NULL, prio_registers, NULL); 101 102 static struct resource rtc_resources[] = { 103 [0] = { 104 .start = 0xa413fec0, 105 .end = 0xa413fec0 + 0x1e, 106 .flags = IORESOURCE_IO, 107 }, 108 [1] = { 109 .start = 20, 110 .flags = IORESOURCE_IRQ, 111 }, 112 [2] = { 113 .start = 21, 114 .flags = IORESOURCE_IRQ, 115 }, 116 [3] = { 117 .start = 22, 118 .flags = IORESOURCE_IRQ, 119 }, 120 }; 121 122 static struct sh_rtc_platform_info rtc_info = { 123 .capabilities = RTC_CAP_4_DIGIT_YEAR, 124 }; 125 126 static struct platform_device rtc_device = { 127 .name = "sh-rtc", 128 .id = -1, 129 .num_resources = ARRAY_SIZE(rtc_resources), 130 .resource = rtc_resources, 131 .dev = { 132 .platform_data = &rtc_info, 133 }, 134 }; 135 136 static struct plat_sci_port sci_platform_data[] = { 137 { 138 .mapbase = 0xa4400000, 139 .flags = UPF_BOOT_AUTOCONF, 140 .type = PORT_SCIF, 141 .irqs = { 52, 53, 55, 54 }, 142 }, { 143 .mapbase = 0xa4410000, 144 .flags = UPF_BOOT_AUTOCONF, 145 .type = PORT_SCIF, 146 .irqs = { 56, 57, 59, 58 }, 147 }, { 148 149 .flags = 0, 150 } 151 }; 152 153 static struct platform_device sci_device = { 154 .name = "sh-sci", 155 .id = -1, 156 .dev = { 157 .platform_data = sci_platform_data, 158 }, 159 }; 160 161 static struct platform_device *sh7710_devices[] __initdata = { 162 &sci_device, 163 &rtc_device, 164 }; 165 166 static int __init sh7710_devices_setup(void) 167 { 168 return platform_add_devices(sh7710_devices, 169 ARRAY_SIZE(sh7710_devices)); 170 } 171 __initcall(sh7710_devices_setup); 172 173 void __init plat_irq_setup_pins(int mode) 174 { 175 if (mode == IRQ_MODE_IRQ) { 176 register_intc_controller(&intc_desc_irq); 177 return; 178 } 179 BUG(); 180 } 181 182 void __init plat_irq_setup(void) 183 { 184 register_intc_controller(&intc_desc); 185 } 186