1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/sh_timer.h> 17 #include <linux/sh_intc.h> 18 #include <asm/rtc.h> 19 20 enum { 21 UNUSED = 0, 22 23 /* interrupt sources */ 24 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 25 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, 26 EDMAC0, EDMAC1, EDMAC2, 27 SIOF0, SIOF1, 28 29 TMU0, TMU1, TMU2, 30 RTC, WDT, REF, 31 }; 32 33 static struct intc_vect vectors[] __initdata = { 34 /* IRQ0->5 are handled in setup-sh3.c */ 35 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), 36 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), 37 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 38 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 39 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), 40 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), 41 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 42 #ifdef CONFIG_CPU_SUBTYPE_SH7710 43 INTC_VECT(IPSEC, 0xbe0), 44 #endif 45 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 46 INTC_VECT(EDMAC2, 0xc40), 47 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), 48 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), 49 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), 50 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), 51 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 52 INTC_VECT(TMU2, 0x440), 53 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 54 INTC_VECT(RTC, 0x4c0), 55 INTC_VECT(WDT, 0x560), 56 INTC_VECT(REF, 0x580), 57 }; 58 59 static struct intc_prio_reg prio_registers[] __initdata = { 60 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 61 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 62 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 63 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 64 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 65 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 66 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 67 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 68 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 69 }; 70 71 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, 72 NULL, prio_registers, NULL); 73 74 static struct resource rtc_resources[] = { 75 [0] = { 76 .start = 0xa413fec0, 77 .end = 0xa413fec0 + 0x1e, 78 .flags = IORESOURCE_IO, 79 }, 80 [1] = { 81 .start = evt2irq(0x480), 82 .flags = IORESOURCE_IRQ, 83 }, 84 }; 85 86 static struct sh_rtc_platform_info rtc_info = { 87 .capabilities = RTC_CAP_4_DIGIT_YEAR, 88 }; 89 90 static struct platform_device rtc_device = { 91 .name = "sh-rtc", 92 .id = -1, 93 .num_resources = ARRAY_SIZE(rtc_resources), 94 .resource = rtc_resources, 95 .dev = { 96 .platform_data = &rtc_info, 97 }, 98 }; 99 100 static struct plat_sci_port scif0_platform_data = { 101 .scscr = SCSCR_REIE | SCSCR_CKE1, 102 .type = PORT_SCIF, 103 }; 104 105 static struct resource scif0_resources[] = { 106 DEFINE_RES_MEM(0xa4400000, 0x100), 107 DEFINE_RES_IRQ(evt2irq(0x880)), 108 }; 109 110 static struct platform_device scif0_device = { 111 .name = "sh-sci", 112 .id = 0, 113 .resource = scif0_resources, 114 .num_resources = ARRAY_SIZE(scif0_resources), 115 .dev = { 116 .platform_data = &scif0_platform_data, 117 }, 118 }; 119 120 static struct plat_sci_port scif1_platform_data = { 121 .scscr = SCSCR_REIE | SCSCR_CKE1, 122 .type = PORT_SCIF, 123 }; 124 125 static struct resource scif1_resources[] = { 126 DEFINE_RES_MEM(0xa4410000, 0x100), 127 DEFINE_RES_IRQ(evt2irq(0x900)), 128 }; 129 130 static struct platform_device scif1_device = { 131 .name = "sh-sci", 132 .id = 1, 133 .resource = scif1_resources, 134 .num_resources = ARRAY_SIZE(scif1_resources), 135 .dev = { 136 .platform_data = &scif1_platform_data, 137 }, 138 }; 139 140 static struct sh_timer_config tmu0_platform_data = { 141 .channels_mask = 7, 142 }; 143 144 static struct resource tmu0_resources[] = { 145 DEFINE_RES_MEM(0xa412fe90, 0x28), 146 DEFINE_RES_IRQ(evt2irq(0x400)), 147 DEFINE_RES_IRQ(evt2irq(0x420)), 148 DEFINE_RES_IRQ(evt2irq(0x440)), 149 }; 150 151 static struct platform_device tmu0_device = { 152 .name = "sh-tmu-sh3", 153 .id = 0, 154 .dev = { 155 .platform_data = &tmu0_platform_data, 156 }, 157 .resource = tmu0_resources, 158 .num_resources = ARRAY_SIZE(tmu0_resources), 159 }; 160 161 static struct platform_device *sh7710_devices[] __initdata = { 162 &scif0_device, 163 &scif1_device, 164 &tmu0_device, 165 &rtc_device, 166 }; 167 168 static int __init sh7710_devices_setup(void) 169 { 170 return platform_add_devices(sh7710_devices, 171 ARRAY_SIZE(sh7710_devices)); 172 } 173 arch_initcall(sh7710_devices_setup); 174 175 static struct platform_device *sh7710_early_devices[] __initdata = { 176 &scif0_device, 177 &scif1_device, 178 &tmu0_device, 179 }; 180 181 void __init plat_early_device_setup(void) 182 { 183 early_platform_add_devices(sh7710_early_devices, 184 ARRAY_SIZE(sh7710_early_devices)); 185 } 186 187 void __init plat_irq_setup(void) 188 { 189 register_intc_controller(&intc_desc); 190 plat_irq_setup_sh3(); 191 } 192