1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <asm/rtc.h> 17 18 enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 23 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, 24 EDMAC0, EDMAC1, EDMAC2, 25 SIOF0, SIOF1, 26 27 TMU0, TMU1, TMU2, 28 RTC, WDT, REF, 29 }; 30 31 static struct intc_vect vectors[] __initdata = { 32 /* IRQ0->5 are handled in setup-sh3.c */ 33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), 34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), 35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), 38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), 39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 40 #ifdef CONFIG_CPU_SUBTYPE_SH7710 41 INTC_VECT(IPSEC, 0xbe0), 42 #endif 43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 44 INTC_VECT(EDMAC2, 0xc40), 45 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), 46 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), 47 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), 48 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), 49 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 50 INTC_VECT(TMU2, 0x440), 51 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 52 INTC_VECT(RTC, 0x4c0), 53 INTC_VECT(WDT, 0x560), 54 INTC_VECT(REF, 0x580), 55 }; 56 57 static struct intc_prio_reg prio_registers[] __initdata = { 58 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 60 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 61 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 62 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 63 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 64 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 65 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 66 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 67 }; 68 69 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, 70 NULL, prio_registers, NULL); 71 72 static struct resource rtc_resources[] = { 73 [0] = { 74 .start = 0xa413fec0, 75 .end = 0xa413fec0 + 0x1e, 76 .flags = IORESOURCE_IO, 77 }, 78 [1] = { 79 .start = 20, 80 .flags = IORESOURCE_IRQ, 81 }, 82 }; 83 84 static struct sh_rtc_platform_info rtc_info = { 85 .capabilities = RTC_CAP_4_DIGIT_YEAR, 86 }; 87 88 static struct platform_device rtc_device = { 89 .name = "sh-rtc", 90 .id = -1, 91 .num_resources = ARRAY_SIZE(rtc_resources), 92 .resource = rtc_resources, 93 .dev = { 94 .platform_data = &rtc_info, 95 }, 96 }; 97 98 static struct plat_sci_port sci_platform_data[] = { 99 { 100 .mapbase = 0xa4400000, 101 .flags = UPF_BOOT_AUTOCONF, 102 .type = PORT_SCIF, 103 .irqs = { 52, 52, 52, 52 }, 104 }, { 105 .mapbase = 0xa4410000, 106 .flags = UPF_BOOT_AUTOCONF, 107 .type = PORT_SCIF, 108 .irqs = { 56, 56, 56, 56 }, 109 }, { 110 111 .flags = 0, 112 } 113 }; 114 115 static struct platform_device sci_device = { 116 .name = "sh-sci", 117 .id = -1, 118 .dev = { 119 .platform_data = sci_platform_data, 120 }, 121 }; 122 123 static struct platform_device *sh7710_devices[] __initdata = { 124 &sci_device, 125 &rtc_device, 126 }; 127 128 static int __init sh7710_devices_setup(void) 129 { 130 return platform_add_devices(sh7710_devices, 131 ARRAY_SIZE(sh7710_devices)); 132 } 133 __initcall(sh7710_devices_setup); 134 135 void __init plat_irq_setup(void) 136 { 137 register_intc_controller(&intc_desc); 138 plat_irq_setup_sh3(); 139 } 140