1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/sh_timer.h> 17 #include <asm/rtc.h> 18 19 enum { 20 UNUSED = 0, 21 22 /* interrupt sources */ 23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 24 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, 25 EDMAC0, EDMAC1, EDMAC2, 26 SIOF0, SIOF1, 27 28 TMU0, TMU1, TMU2, 29 RTC, WDT, REF, 30 }; 31 32 static struct intc_vect vectors[] __initdata = { 33 /* IRQ0->5 are handled in setup-sh3.c */ 34 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), 35 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), 36 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 37 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 38 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), 39 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), 40 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 41 #ifdef CONFIG_CPU_SUBTYPE_SH7710 42 INTC_VECT(IPSEC, 0xbe0), 43 #endif 44 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 45 INTC_VECT(EDMAC2, 0xc40), 46 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), 47 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), 48 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), 49 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), 50 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 51 INTC_VECT(TMU2, 0x440), 52 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 53 INTC_VECT(RTC, 0x4c0), 54 INTC_VECT(WDT, 0x560), 55 INTC_VECT(REF, 0x580), 56 }; 57 58 static struct intc_prio_reg prio_registers[] __initdata = { 59 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 60 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 61 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 62 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 63 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 64 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 65 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 66 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 67 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 68 }; 69 70 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, 71 NULL, prio_registers, NULL); 72 73 static struct resource rtc_resources[] = { 74 [0] = { 75 .start = 0xa413fec0, 76 .end = 0xa413fec0 + 0x1e, 77 .flags = IORESOURCE_IO, 78 }, 79 [1] = { 80 .start = 20, 81 .flags = IORESOURCE_IRQ, 82 }, 83 }; 84 85 static struct sh_rtc_platform_info rtc_info = { 86 .capabilities = RTC_CAP_4_DIGIT_YEAR, 87 }; 88 89 static struct platform_device rtc_device = { 90 .name = "sh-rtc", 91 .id = -1, 92 .num_resources = ARRAY_SIZE(rtc_resources), 93 .resource = rtc_resources, 94 .dev = { 95 .platform_data = &rtc_info, 96 }, 97 }; 98 99 static struct plat_sci_port scif0_platform_data = { 100 .mapbase = 0xa4400000, 101 .flags = UPF_BOOT_AUTOCONF, 102 .type = PORT_SCIF, 103 .irqs = { 52, 52, 52, 52 }, 104 }; 105 106 static struct platform_device scif0_device = { 107 .name = "sh-sci", 108 .id = 0, 109 .dev = { 110 .platform_data = &scif0_platform_data, 111 }, 112 }; 113 114 static struct plat_sci_port scif1_platform_data = { 115 .mapbase = 0xa4410000, 116 .flags = UPF_BOOT_AUTOCONF, 117 .type = PORT_SCIF, 118 .irqs = { 56, 56, 56, 56 }, 119 }; 120 121 static struct platform_device scif1_device = { 122 .name = "sh-sci", 123 .id = 1, 124 .dev = { 125 .platform_data = &scif1_platform_data, 126 }, 127 }; 128 129 static struct sh_timer_config tmu0_platform_data = { 130 .name = "TMU0", 131 .channel_offset = 0x02, 132 .timer_bit = 0, 133 .clk = "peripheral_clk", 134 .clockevent_rating = 200, 135 }; 136 137 static struct resource tmu0_resources[] = { 138 [0] = { 139 .name = "TMU0", 140 .start = 0xa412fe94, 141 .end = 0xa412fe9f, 142 .flags = IORESOURCE_MEM, 143 }, 144 [1] = { 145 .start = 16, 146 .flags = IORESOURCE_IRQ, 147 }, 148 }; 149 150 static struct platform_device tmu0_device = { 151 .name = "sh_tmu", 152 .id = 0, 153 .dev = { 154 .platform_data = &tmu0_platform_data, 155 }, 156 .resource = tmu0_resources, 157 .num_resources = ARRAY_SIZE(tmu0_resources), 158 }; 159 160 static struct sh_timer_config tmu1_platform_data = { 161 .name = "TMU1", 162 .channel_offset = 0xe, 163 .timer_bit = 1, 164 .clk = "peripheral_clk", 165 .clocksource_rating = 200, 166 }; 167 168 static struct resource tmu1_resources[] = { 169 [0] = { 170 .name = "TMU1", 171 .start = 0xa412fea0, 172 .end = 0xa412feab, 173 .flags = IORESOURCE_MEM, 174 }, 175 [1] = { 176 .start = 17, 177 .flags = IORESOURCE_IRQ, 178 }, 179 }; 180 181 static struct platform_device tmu1_device = { 182 .name = "sh_tmu", 183 .id = 1, 184 .dev = { 185 .platform_data = &tmu1_platform_data, 186 }, 187 .resource = tmu1_resources, 188 .num_resources = ARRAY_SIZE(tmu1_resources), 189 }; 190 191 static struct sh_timer_config tmu2_platform_data = { 192 .name = "TMU2", 193 .channel_offset = 0x1a, 194 .timer_bit = 2, 195 .clk = "peripheral_clk", 196 }; 197 198 static struct resource tmu2_resources[] = { 199 [0] = { 200 .name = "TMU2", 201 .start = 0xa412feac, 202 .end = 0xa412feb5, 203 .flags = IORESOURCE_MEM, 204 }, 205 [1] = { 206 .start = 18, 207 .flags = IORESOURCE_IRQ, 208 }, 209 }; 210 211 static struct platform_device tmu2_device = { 212 .name = "sh_tmu", 213 .id = 2, 214 .dev = { 215 .platform_data = &tmu2_platform_data, 216 }, 217 .resource = tmu2_resources, 218 .num_resources = ARRAY_SIZE(tmu2_resources), 219 }; 220 221 static struct platform_device *sh7710_devices[] __initdata = { 222 &scif0_device, 223 &scif1_device, 224 &tmu0_device, 225 &tmu1_device, 226 &tmu2_device, 227 &rtc_device, 228 }; 229 230 static int __init sh7710_devices_setup(void) 231 { 232 return platform_add_devices(sh7710_devices, 233 ARRAY_SIZE(sh7710_devices)); 234 } 235 arch_initcall(sh7710_devices_setup); 236 237 static struct platform_device *sh7710_early_devices[] __initdata = { 238 &scif0_device, 239 &scif1_device, 240 &tmu0_device, 241 &tmu1_device, 242 &tmu2_device, 243 }; 244 245 void __init plat_early_device_setup(void) 246 { 247 early_platform_add_devices(sh7710_early_devices, 248 ARRAY_SIZE(sh7710_early_devices)); 249 } 250 251 void __init plat_irq_setup(void) 252 { 253 register_intc_controller(&intc_desc); 254 plat_irq_setup_sh3(); 255 } 256