1 /* 2 * SH3 Setup code for SH7710, SH7712 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/serial.h> 15 #include <linux/serial_sci.h> 16 #include <linux/sh_timer.h> 17 #include <asm/rtc.h> 18 19 enum { 20 UNUSED = 0, 21 22 /* interrupt sources */ 23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 24 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, 25 EDMAC0, EDMAC1, EDMAC2, 26 SIOF0, SIOF1, 27 28 TMU0, TMU1, TMU2, 29 RTC, WDT, REF, 30 }; 31 32 static struct intc_vect vectors[] __initdata = { 33 /* IRQ0->5 are handled in setup-sh3.c */ 34 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), 35 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), 36 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 37 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 38 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), 39 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), 40 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), 41 #ifdef CONFIG_CPU_SUBTYPE_SH7710 42 INTC_VECT(IPSEC, 0xbe0), 43 #endif 44 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 45 INTC_VECT(EDMAC2, 0xc40), 46 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), 47 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), 48 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), 49 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), 50 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 51 INTC_VECT(TMU2, 0x440), 52 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 53 INTC_VECT(RTC, 0x4c0), 54 INTC_VECT(WDT, 0x560), 55 INTC_VECT(REF, 0x580), 56 }; 57 58 static struct intc_prio_reg prio_registers[] __initdata = { 59 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 60 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 61 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 62 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 63 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, 64 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, 65 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, 66 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, 67 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 68 }; 69 70 static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL, 71 NULL, prio_registers, NULL); 72 73 static struct resource rtc_resources[] = { 74 [0] = { 75 .start = 0xa413fec0, 76 .end = 0xa413fec0 + 0x1e, 77 .flags = IORESOURCE_IO, 78 }, 79 [1] = { 80 .start = 20, 81 .flags = IORESOURCE_IRQ, 82 }, 83 }; 84 85 static struct sh_rtc_platform_info rtc_info = { 86 .capabilities = RTC_CAP_4_DIGIT_YEAR, 87 }; 88 89 static struct platform_device rtc_device = { 90 .name = "sh-rtc", 91 .id = -1, 92 .num_resources = ARRAY_SIZE(rtc_resources), 93 .resource = rtc_resources, 94 .dev = { 95 .platform_data = &rtc_info, 96 }, 97 }; 98 99 static struct plat_sci_port sci_platform_data[] = { 100 { 101 .mapbase = 0xa4400000, 102 .flags = UPF_BOOT_AUTOCONF, 103 .type = PORT_SCIF, 104 .irqs = { 52, 52, 52, 52 }, 105 }, { 106 .mapbase = 0xa4410000, 107 .flags = UPF_BOOT_AUTOCONF, 108 .type = PORT_SCIF, 109 .irqs = { 56, 56, 56, 56 }, 110 }, { 111 112 .flags = 0, 113 } 114 }; 115 116 static struct platform_device sci_device = { 117 .name = "sh-sci", 118 .id = -1, 119 .dev = { 120 .platform_data = sci_platform_data, 121 }, 122 }; 123 124 static struct sh_timer_config tmu0_platform_data = { 125 .name = "TMU0", 126 .channel_offset = 0x02, 127 .timer_bit = 0, 128 .clk = "peripheral_clk", 129 .clockevent_rating = 200, 130 }; 131 132 static struct resource tmu0_resources[] = { 133 [0] = { 134 .name = "TMU0", 135 .start = 0xa412fe94, 136 .end = 0xa412fe9f, 137 .flags = IORESOURCE_MEM, 138 }, 139 [1] = { 140 .start = 16, 141 .flags = IORESOURCE_IRQ, 142 }, 143 }; 144 145 static struct platform_device tmu0_device = { 146 .name = "sh_tmu", 147 .id = 0, 148 .dev = { 149 .platform_data = &tmu0_platform_data, 150 }, 151 .resource = tmu0_resources, 152 .num_resources = ARRAY_SIZE(tmu0_resources), 153 }; 154 155 static struct sh_timer_config tmu1_platform_data = { 156 .name = "TMU1", 157 .channel_offset = 0xe, 158 .timer_bit = 1, 159 .clk = "peripheral_clk", 160 .clocksource_rating = 200, 161 }; 162 163 static struct resource tmu1_resources[] = { 164 [0] = { 165 .name = "TMU1", 166 .start = 0xa412fea0, 167 .end = 0xa412feab, 168 .flags = IORESOURCE_MEM, 169 }, 170 [1] = { 171 .start = 17, 172 .flags = IORESOURCE_IRQ, 173 }, 174 }; 175 176 static struct platform_device tmu1_device = { 177 .name = "sh_tmu", 178 .id = 1, 179 .dev = { 180 .platform_data = &tmu1_platform_data, 181 }, 182 .resource = tmu1_resources, 183 .num_resources = ARRAY_SIZE(tmu1_resources), 184 }; 185 186 static struct sh_timer_config tmu2_platform_data = { 187 .name = "TMU2", 188 .channel_offset = 0x1a, 189 .timer_bit = 2, 190 .clk = "peripheral_clk", 191 }; 192 193 static struct resource tmu2_resources[] = { 194 [0] = { 195 .name = "TMU2", 196 .start = 0xa412feac, 197 .end = 0xa412feb5, 198 .flags = IORESOURCE_MEM, 199 }, 200 [1] = { 201 .start = 18, 202 .flags = IORESOURCE_IRQ, 203 }, 204 }; 205 206 static struct platform_device tmu2_device = { 207 .name = "sh_tmu", 208 .id = 2, 209 .dev = { 210 .platform_data = &tmu2_platform_data, 211 }, 212 .resource = tmu2_resources, 213 .num_resources = ARRAY_SIZE(tmu2_resources), 214 }; 215 216 static struct platform_device *sh7710_devices[] __initdata = { 217 &tmu0_device, 218 &tmu1_device, 219 &tmu2_device, 220 &sci_device, 221 &rtc_device, 222 }; 223 224 static int __init sh7710_devices_setup(void) 225 { 226 return platform_add_devices(sh7710_devices, 227 ARRAY_SIZE(sh7710_devices)); 228 } 229 __initcall(sh7710_devices_setup); 230 231 static struct platform_device *sh7710_early_devices[] __initdata = { 232 &tmu0_device, 233 &tmu1_device, 234 &tmu2_device, 235 }; 236 237 void __init plat_early_device_setup(void) 238 { 239 early_platform_add_devices(sh7710_early_devices, 240 ARRAY_SIZE(sh7710_early_devices)); 241 } 242 243 void __init plat_irq_setup(void) 244 { 245 register_intc_controller(&intc_desc); 246 plat_irq_setup_sh3(); 247 } 248