1 /* 2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 3 * 4 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on setup-sh7709.c 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/serial.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 23 enum { 24 UNUSED = 0, 25 26 /* interrupt sources */ 27 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 28 PINT07, PINT815, 29 DMAC, SCIF0, SCIF2, SCI, ADC_ADI, 30 LCDC, PCC0, PCC1, 31 TMU0, TMU1, TMU2, 32 RTC, WDT, REF, 33 }; 34 35 static struct intc_vect vectors[] __initdata = { 36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 39 INTC_VECT(RTC, 0x4c0), 40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), 41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), 42 INTC_VECT(WDT, 0x560), 43 INTC_VECT(REF, 0x580), 44 INTC_VECT(REF, 0x5a0), 45 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 46 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 47 defined(CONFIG_CPU_SUBTYPE_SH7709) 48 /* IRQ0->5 are handled in setup-sh3.c */ 49 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), 50 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), 51 INTC_VECT(ADC_ADI, 0x980), 52 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), 53 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), 54 #endif 55 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 56 defined(CONFIG_CPU_SUBTYPE_SH7709) 57 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 58 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 59 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 60 #endif 61 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 62 INTC_VECT(LCDC, 0x9a0), 63 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0), 64 #endif 65 }; 66 67 static struct intc_prio_reg prio_registers[] __initdata = { 68 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 69 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 70 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 71 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 72 defined(CONFIG_CPU_SUBTYPE_SH7709) 73 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 74 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 75 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, 76 #endif 77 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 78 defined(CONFIG_CPU_SUBTYPE_SH7709) 79 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } }, 80 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } }, 81 #endif 82 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 83 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, 84 #endif 85 }; 86 87 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, 88 NULL, prio_registers, NULL); 89 90 static struct resource rtc_resources[] = { 91 [0] = { 92 .start = 0xfffffec0, 93 .end = 0xfffffec0 + 0x1e, 94 .flags = IORESOURCE_IO, 95 }, 96 [1] = { 97 .start = 20, 98 .flags = IORESOURCE_IRQ, 99 }, 100 }; 101 102 static struct platform_device rtc_device = { 103 .name = "sh-rtc", 104 .id = -1, 105 .num_resources = ARRAY_SIZE(rtc_resources), 106 .resource = rtc_resources, 107 }; 108 109 static struct plat_sci_port scif0_platform_data = { 110 .mapbase = 0xfffffe80, 111 .flags = UPF_BOOT_AUTOCONF, 112 .type = PORT_SCI, 113 .irqs = { 23, 23, 23, 0 }, 114 }; 115 116 static struct platform_device scif0_device = { 117 .name = "sh-sci", 118 .id = 0, 119 .dev = { 120 .platform_data = &scif0_platform_data, 121 }, 122 }; 123 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 124 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 125 defined(CONFIG_CPU_SUBTYPE_SH7709) 126 static struct plat_sci_port scif1_platform_data = { 127 .mapbase = 0xa4000150, 128 .flags = UPF_BOOT_AUTOCONF, 129 .type = PORT_SCIF, 130 .irqs = { 56, 56, 56, 56 }, 131 }; 132 133 static struct platform_device scif1_device = { 134 .name = "sh-sci", 135 .id = 1, 136 .dev = { 137 .platform_data = &scif1_platform_data, 138 }, 139 }; 140 #endif 141 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 142 defined(CONFIG_CPU_SUBTYPE_SH7709) 143 static struct plat_sci_port scif2_platform_data = { 144 .mapbase = 0xa4000140, 145 .flags = UPF_BOOT_AUTOCONF, 146 .type = PORT_IRDA, 147 .irqs = { 52, 52, 52, 52 }, 148 }; 149 150 static struct platform_device scif2_device = { 151 .name = "sh-sci", 152 .id = 2, 153 .dev = { 154 .platform_data = &scif2_platform_data, 155 }, 156 }; 157 #endif 158 159 static struct sh_timer_config tmu0_platform_data = { 160 .channel_offset = 0x02, 161 .timer_bit = 0, 162 .clockevent_rating = 200, 163 }; 164 165 static struct resource tmu0_resources[] = { 166 [0] = { 167 .start = 0xfffffe94, 168 .end = 0xfffffe9f, 169 .flags = IORESOURCE_MEM, 170 }, 171 [1] = { 172 .start = 16, 173 .flags = IORESOURCE_IRQ, 174 }, 175 }; 176 177 static struct platform_device tmu0_device = { 178 .name = "sh_tmu", 179 .id = 0, 180 .dev = { 181 .platform_data = &tmu0_platform_data, 182 }, 183 .resource = tmu0_resources, 184 .num_resources = ARRAY_SIZE(tmu0_resources), 185 }; 186 187 static struct sh_timer_config tmu1_platform_data = { 188 .channel_offset = 0xe, 189 .timer_bit = 1, 190 .clocksource_rating = 200, 191 }; 192 193 static struct resource tmu1_resources[] = { 194 [0] = { 195 .start = 0xfffffea0, 196 .end = 0xfffffeab, 197 .flags = IORESOURCE_MEM, 198 }, 199 [1] = { 200 .start = 17, 201 .flags = IORESOURCE_IRQ, 202 }, 203 }; 204 205 static struct platform_device tmu1_device = { 206 .name = "sh_tmu", 207 .id = 1, 208 .dev = { 209 .platform_data = &tmu1_platform_data, 210 }, 211 .resource = tmu1_resources, 212 .num_resources = ARRAY_SIZE(tmu1_resources), 213 }; 214 215 static struct sh_timer_config tmu2_platform_data = { 216 .channel_offset = 0x1a, 217 .timer_bit = 2, 218 }; 219 220 static struct resource tmu2_resources[] = { 221 [0] = { 222 .start = 0xfffffeac, 223 .end = 0xfffffebb, 224 .flags = IORESOURCE_MEM, 225 }, 226 [1] = { 227 .start = 18, 228 .flags = IORESOURCE_IRQ, 229 }, 230 }; 231 232 static struct platform_device tmu2_device = { 233 .name = "sh_tmu", 234 .id = 2, 235 .dev = { 236 .platform_data = &tmu2_platform_data, 237 }, 238 .resource = tmu2_resources, 239 .num_resources = ARRAY_SIZE(tmu2_resources), 240 }; 241 242 static struct platform_device *sh770x_devices[] __initdata = { 243 &scif0_device, 244 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 245 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 246 defined(CONFIG_CPU_SUBTYPE_SH7709) 247 &scif1_device, 248 #endif 249 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 250 defined(CONFIG_CPU_SUBTYPE_SH7709) 251 &scif2_device, 252 #endif 253 &tmu0_device, 254 &tmu1_device, 255 &tmu2_device, 256 &rtc_device, 257 }; 258 259 static int __init sh770x_devices_setup(void) 260 { 261 return platform_add_devices(sh770x_devices, 262 ARRAY_SIZE(sh770x_devices)); 263 } 264 arch_initcall(sh770x_devices_setup); 265 266 static struct platform_device *sh770x_early_devices[] __initdata = { 267 &scif0_device, 268 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 269 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 270 defined(CONFIG_CPU_SUBTYPE_SH7709) 271 &scif1_device, 272 #endif 273 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 274 defined(CONFIG_CPU_SUBTYPE_SH7709) 275 &scif2_device, 276 #endif 277 &tmu0_device, 278 &tmu1_device, 279 &tmu2_device, 280 }; 281 282 void __init plat_early_device_setup(void) 283 { 284 early_platform_add_devices(sh770x_early_devices, 285 ARRAY_SIZE(sh770x_early_devices)); 286 } 287 288 void __init plat_irq_setup(void) 289 { 290 register_intc_controller(&intc_desc); 291 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 292 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 293 defined(CONFIG_CPU_SUBTYPE_SH7709) 294 plat_irq_setup_sh3(); 295 #endif 296 } 297