1 /* 2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 3 * 4 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on setup-sh7709.c 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/serial.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <linux/sh_intc.h> 23 #include <cpu/serial.h> 24 25 enum { 26 UNUSED = 0, 27 28 /* interrupt sources */ 29 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 30 PINT07, PINT815, 31 DMAC, SCIF0, SCIF2, SCI, ADC_ADI, 32 LCDC, PCC0, PCC1, 33 TMU0, TMU1, TMU2, 34 RTC, WDT, REF, 35 }; 36 37 static struct intc_vect vectors[] __initdata = { 38 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 39 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 40 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 41 INTC_VECT(RTC, 0x4c0), 42 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), 43 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), 44 INTC_VECT(WDT, 0x560), 45 INTC_VECT(REF, 0x580), 46 INTC_VECT(REF, 0x5a0), 47 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 48 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 49 defined(CONFIG_CPU_SUBTYPE_SH7709) 50 /* IRQ0->5 are handled in setup-sh3.c */ 51 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), 52 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), 53 INTC_VECT(ADC_ADI, 0x980), 54 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), 55 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), 56 #endif 57 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 58 defined(CONFIG_CPU_SUBTYPE_SH7709) 59 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 60 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 61 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 62 #endif 63 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 64 INTC_VECT(LCDC, 0x9a0), 65 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0), 66 #endif 67 }; 68 69 static struct intc_prio_reg prio_registers[] __initdata = { 70 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 72 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 73 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 74 defined(CONFIG_CPU_SUBTYPE_SH7709) 75 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 76 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 77 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, 78 #endif 79 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 80 defined(CONFIG_CPU_SUBTYPE_SH7709) 81 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } }, 82 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } }, 83 #endif 84 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 85 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, 86 #endif 87 }; 88 89 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, 90 NULL, prio_registers, NULL); 91 92 static struct resource rtc_resources[] = { 93 [0] = { 94 .start = 0xfffffec0, 95 .end = 0xfffffec0 + 0x1e, 96 .flags = IORESOURCE_IO, 97 }, 98 [1] = { 99 .start = evt2irq(0x480), 100 .flags = IORESOURCE_IRQ, 101 }, 102 }; 103 104 static struct platform_device rtc_device = { 105 .name = "sh-rtc", 106 .id = -1, 107 .num_resources = ARRAY_SIZE(rtc_resources), 108 .resource = rtc_resources, 109 }; 110 111 static struct plat_sci_port scif0_platform_data = { 112 .port_reg = 0xa4000136, 113 .flags = UPF_BOOT_AUTOCONF, 114 .scscr = SCSCR_TE | SCSCR_RE, 115 .type = PORT_SCI, 116 .ops = &sh770x_sci_port_ops, 117 .regshift = 1, 118 }; 119 120 static struct resource scif0_resources[] = { 121 DEFINE_RES_MEM(0xfffffe80, 0x100), 122 DEFINE_RES_IRQ(evt2irq(0x4e0)), 123 }; 124 125 static struct platform_device scif0_device = { 126 .name = "sh-sci", 127 .id = 0, 128 .resource = scif0_resources, 129 .num_resources = ARRAY_SIZE(scif0_resources), 130 .dev = { 131 .platform_data = &scif0_platform_data, 132 }, 133 }; 134 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 135 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 136 defined(CONFIG_CPU_SUBTYPE_SH7709) 137 static struct plat_sci_port scif1_platform_data = { 138 .flags = UPF_BOOT_AUTOCONF, 139 .scscr = SCSCR_TE | SCSCR_RE, 140 .type = PORT_SCIF, 141 .ops = &sh770x_sci_port_ops, 142 .regtype = SCIx_SH3_SCIF_REGTYPE, 143 }; 144 145 static struct resource scif1_resources[] = { 146 DEFINE_RES_MEM(0xa4000150, 0x100), 147 DEFINE_RES_IRQ(evt2irq(0x900)), 148 }; 149 150 static struct platform_device scif1_device = { 151 .name = "sh-sci", 152 .id = 1, 153 .resource = scif1_resources, 154 .num_resources = ARRAY_SIZE(scif1_resources), 155 .dev = { 156 .platform_data = &scif1_platform_data, 157 }, 158 }; 159 #endif 160 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 161 defined(CONFIG_CPU_SUBTYPE_SH7709) 162 static struct plat_sci_port scif2_platform_data = { 163 .port_reg = SCIx_NOT_SUPPORTED, 164 .flags = UPF_BOOT_AUTOCONF, 165 .scscr = SCSCR_TE | SCSCR_RE, 166 .type = PORT_IRDA, 167 .ops = &sh770x_sci_port_ops, 168 .regshift = 1, 169 }; 170 171 static struct resource scif2_resources[] = { 172 DEFINE_RES_MEM(0xa4000140, 0x100), 173 DEFINE_RES_IRQ(evt2irq(0x880)), 174 }; 175 176 static struct platform_device scif2_device = { 177 .name = "sh-sci", 178 .id = 2, 179 .resource = scif2_resources, 180 .num_resources = ARRAY_SIZE(scif2_resources), 181 .dev = { 182 .platform_data = &scif2_platform_data, 183 }, 184 }; 185 #endif 186 187 static struct sh_timer_config tmu0_platform_data = { 188 .channel_offset = 0x02, 189 .timer_bit = 0, 190 .clockevent_rating = 200, 191 }; 192 193 static struct resource tmu0_resources[] = { 194 [0] = { 195 .start = 0xfffffe94, 196 .end = 0xfffffe9f, 197 .flags = IORESOURCE_MEM, 198 }, 199 [1] = { 200 .start = evt2irq(0x400), 201 .flags = IORESOURCE_IRQ, 202 }, 203 }; 204 205 static struct platform_device tmu0_device = { 206 .name = "sh_tmu", 207 .id = 0, 208 .dev = { 209 .platform_data = &tmu0_platform_data, 210 }, 211 .resource = tmu0_resources, 212 .num_resources = ARRAY_SIZE(tmu0_resources), 213 }; 214 215 static struct sh_timer_config tmu1_platform_data = { 216 .channel_offset = 0xe, 217 .timer_bit = 1, 218 .clocksource_rating = 200, 219 }; 220 221 static struct resource tmu1_resources[] = { 222 [0] = { 223 .start = 0xfffffea0, 224 .end = 0xfffffeab, 225 .flags = IORESOURCE_MEM, 226 }, 227 [1] = { 228 .start = evt2irq(0x420), 229 .flags = IORESOURCE_IRQ, 230 }, 231 }; 232 233 static struct platform_device tmu1_device = { 234 .name = "sh_tmu", 235 .id = 1, 236 .dev = { 237 .platform_data = &tmu1_platform_data, 238 }, 239 .resource = tmu1_resources, 240 .num_resources = ARRAY_SIZE(tmu1_resources), 241 }; 242 243 static struct sh_timer_config tmu2_platform_data = { 244 .channel_offset = 0x1a, 245 .timer_bit = 2, 246 }; 247 248 static struct resource tmu2_resources[] = { 249 [0] = { 250 .start = 0xfffffeac, 251 .end = 0xfffffebb, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { 255 .start = evt2irq(0x440), 256 .flags = IORESOURCE_IRQ, 257 }, 258 }; 259 260 static struct platform_device tmu2_device = { 261 .name = "sh_tmu", 262 .id = 2, 263 .dev = { 264 .platform_data = &tmu2_platform_data, 265 }, 266 .resource = tmu2_resources, 267 .num_resources = ARRAY_SIZE(tmu2_resources), 268 }; 269 270 static struct platform_device *sh770x_devices[] __initdata = { 271 &scif0_device, 272 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 273 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 274 defined(CONFIG_CPU_SUBTYPE_SH7709) 275 &scif1_device, 276 #endif 277 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 278 defined(CONFIG_CPU_SUBTYPE_SH7709) 279 &scif2_device, 280 #endif 281 &tmu0_device, 282 &tmu1_device, 283 &tmu2_device, 284 &rtc_device, 285 }; 286 287 static int __init sh770x_devices_setup(void) 288 { 289 return platform_add_devices(sh770x_devices, 290 ARRAY_SIZE(sh770x_devices)); 291 } 292 arch_initcall(sh770x_devices_setup); 293 294 static struct platform_device *sh770x_early_devices[] __initdata = { 295 &scif0_device, 296 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 297 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 298 defined(CONFIG_CPU_SUBTYPE_SH7709) 299 &scif1_device, 300 #endif 301 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 302 defined(CONFIG_CPU_SUBTYPE_SH7709) 303 &scif2_device, 304 #endif 305 &tmu0_device, 306 &tmu1_device, 307 &tmu2_device, 308 }; 309 310 void __init plat_early_device_setup(void) 311 { 312 early_platform_add_devices(sh770x_early_devices, 313 ARRAY_SIZE(sh770x_early_devices)); 314 } 315 316 void __init plat_irq_setup(void) 317 { 318 register_intc_controller(&intc_desc); 319 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 320 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 321 defined(CONFIG_CPU_SUBTYPE_SH7709) 322 plat_irq_setup_sh3(); 323 #endif 324 } 325