1 /* 2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 3 * 4 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * Based on setup-sh7709.c 8 * 9 * Copyright (C) 2006 Paul Mundt 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/serial.h> 20 #include <linux/serial_sci.h> 21 #include <linux/sh_timer.h> 22 #include <linux/sh_intc.h> 23 #include <cpu/serial.h> 24 25 enum { 26 UNUSED = 0, 27 28 /* interrupt sources */ 29 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 30 PINT07, PINT815, 31 DMAC, SCIF0, SCIF2, SCI, ADC_ADI, 32 LCDC, PCC0, PCC1, 33 TMU0, TMU1, TMU2, 34 RTC, WDT, REF, 35 }; 36 37 static struct intc_vect vectors[] __initdata = { 38 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 39 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), 40 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), 41 INTC_VECT(RTC, 0x4c0), 42 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), 43 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), 44 INTC_VECT(WDT, 0x560), 45 INTC_VECT(REF, 0x580), 46 INTC_VECT(REF, 0x5a0), 47 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 48 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 49 defined(CONFIG_CPU_SUBTYPE_SH7709) 50 /* IRQ0->5 are handled in setup-sh3.c */ 51 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), 52 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), 53 INTC_VECT(ADC_ADI, 0x980), 54 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), 55 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), 56 #endif 57 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 58 defined(CONFIG_CPU_SUBTYPE_SH7709) 59 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 60 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), 61 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), 62 #endif 63 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 64 INTC_VECT(LCDC, 0x9a0), 65 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0), 66 #endif 67 }; 68 69 static struct intc_prio_reg prio_registers[] __initdata = { 70 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 72 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 73 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 74 defined(CONFIG_CPU_SUBTYPE_SH7709) 75 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 76 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 77 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, 78 #endif 79 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 80 defined(CONFIG_CPU_SUBTYPE_SH7709) 81 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } }, 82 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } }, 83 #endif 84 #if defined(CONFIG_CPU_SUBTYPE_SH7707) 85 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, 86 #endif 87 }; 88 89 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, 90 NULL, prio_registers, NULL); 91 92 static struct resource rtc_resources[] = { 93 [0] = { 94 .start = 0xfffffec0, 95 .end = 0xfffffec0 + 0x1e, 96 .flags = IORESOURCE_IO, 97 }, 98 [1] = { 99 .start = evt2irq(0x480), 100 .flags = IORESOURCE_IRQ, 101 }, 102 }; 103 104 static struct platform_device rtc_device = { 105 .name = "sh-rtc", 106 .id = -1, 107 .num_resources = ARRAY_SIZE(rtc_resources), 108 .resource = rtc_resources, 109 }; 110 111 static struct plat_sci_port scif0_platform_data = { 112 .mapbase = 0xfffffe80, 113 .port_reg = 0xa4000136, 114 .flags = UPF_BOOT_AUTOCONF, 115 .scscr = SCSCR_TE | SCSCR_RE, 116 .scbrr_algo_id = SCBRR_ALGO_2, 117 .type = PORT_SCI, 118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), 119 .ops = &sh770x_sci_port_ops, 120 .regshift = 1, 121 }; 122 123 static struct platform_device scif0_device = { 124 .name = "sh-sci", 125 .id = 0, 126 .dev = { 127 .platform_data = &scif0_platform_data, 128 }, 129 }; 130 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 131 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 132 defined(CONFIG_CPU_SUBTYPE_SH7709) 133 static struct plat_sci_port scif1_platform_data = { 134 .mapbase = 0xa4000150, 135 .flags = UPF_BOOT_AUTOCONF, 136 .scscr = SCSCR_TE | SCSCR_RE, 137 .scbrr_algo_id = SCBRR_ALGO_2, 138 .type = PORT_SCIF, 139 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 140 .ops = &sh770x_sci_port_ops, 141 .regtype = SCIx_SH3_SCIF_REGTYPE, 142 }; 143 144 static struct platform_device scif1_device = { 145 .name = "sh-sci", 146 .id = 1, 147 .dev = { 148 .platform_data = &scif1_platform_data, 149 }, 150 }; 151 #endif 152 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 153 defined(CONFIG_CPU_SUBTYPE_SH7709) 154 static struct plat_sci_port scif2_platform_data = { 155 .mapbase = 0xa4000140, 156 .port_reg = SCIx_NOT_SUPPORTED, 157 .flags = UPF_BOOT_AUTOCONF, 158 .scscr = SCSCR_TE | SCSCR_RE, 159 .scbrr_algo_id = SCBRR_ALGO_2, 160 .type = PORT_IRDA, 161 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), 162 .ops = &sh770x_sci_port_ops, 163 .regshift = 1, 164 }; 165 166 static struct platform_device scif2_device = { 167 .name = "sh-sci", 168 .id = 2, 169 .dev = { 170 .platform_data = &scif2_platform_data, 171 }, 172 }; 173 #endif 174 175 static struct sh_timer_config tmu0_platform_data = { 176 .channel_offset = 0x02, 177 .timer_bit = 0, 178 .clockevent_rating = 200, 179 }; 180 181 static struct resource tmu0_resources[] = { 182 [0] = { 183 .start = 0xfffffe94, 184 .end = 0xfffffe9f, 185 .flags = IORESOURCE_MEM, 186 }, 187 [1] = { 188 .start = evt2irq(0x400), 189 .flags = IORESOURCE_IRQ, 190 }, 191 }; 192 193 static struct platform_device tmu0_device = { 194 .name = "sh_tmu", 195 .id = 0, 196 .dev = { 197 .platform_data = &tmu0_platform_data, 198 }, 199 .resource = tmu0_resources, 200 .num_resources = ARRAY_SIZE(tmu0_resources), 201 }; 202 203 static struct sh_timer_config tmu1_platform_data = { 204 .channel_offset = 0xe, 205 .timer_bit = 1, 206 .clocksource_rating = 200, 207 }; 208 209 static struct resource tmu1_resources[] = { 210 [0] = { 211 .start = 0xfffffea0, 212 .end = 0xfffffeab, 213 .flags = IORESOURCE_MEM, 214 }, 215 [1] = { 216 .start = evt2irq(0x420), 217 .flags = IORESOURCE_IRQ, 218 }, 219 }; 220 221 static struct platform_device tmu1_device = { 222 .name = "sh_tmu", 223 .id = 1, 224 .dev = { 225 .platform_data = &tmu1_platform_data, 226 }, 227 .resource = tmu1_resources, 228 .num_resources = ARRAY_SIZE(tmu1_resources), 229 }; 230 231 static struct sh_timer_config tmu2_platform_data = { 232 .channel_offset = 0x1a, 233 .timer_bit = 2, 234 }; 235 236 static struct resource tmu2_resources[] = { 237 [0] = { 238 .start = 0xfffffeac, 239 .end = 0xfffffebb, 240 .flags = IORESOURCE_MEM, 241 }, 242 [1] = { 243 .start = evt2irq(0x440), 244 .flags = IORESOURCE_IRQ, 245 }, 246 }; 247 248 static struct platform_device tmu2_device = { 249 .name = "sh_tmu", 250 .id = 2, 251 .dev = { 252 .platform_data = &tmu2_platform_data, 253 }, 254 .resource = tmu2_resources, 255 .num_resources = ARRAY_SIZE(tmu2_resources), 256 }; 257 258 static struct platform_device *sh770x_devices[] __initdata = { 259 &scif0_device, 260 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 261 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 262 defined(CONFIG_CPU_SUBTYPE_SH7709) 263 &scif1_device, 264 #endif 265 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 266 defined(CONFIG_CPU_SUBTYPE_SH7709) 267 &scif2_device, 268 #endif 269 &tmu0_device, 270 &tmu1_device, 271 &tmu2_device, 272 &rtc_device, 273 }; 274 275 static int __init sh770x_devices_setup(void) 276 { 277 return platform_add_devices(sh770x_devices, 278 ARRAY_SIZE(sh770x_devices)); 279 } 280 arch_initcall(sh770x_devices_setup); 281 282 static struct platform_device *sh770x_early_devices[] __initdata = { 283 &scif0_device, 284 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 285 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 286 defined(CONFIG_CPU_SUBTYPE_SH7709) 287 &scif1_device, 288 #endif 289 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 290 defined(CONFIG_CPU_SUBTYPE_SH7709) 291 &scif2_device, 292 #endif 293 &tmu0_device, 294 &tmu1_device, 295 &tmu2_device, 296 }; 297 298 void __init plat_early_device_setup(void) 299 { 300 early_platform_add_devices(sh770x_early_devices, 301 ARRAY_SIZE(sh770x_early_devices)); 302 } 303 304 void __init plat_irq_setup(void) 305 { 306 register_intc_controller(&intc_desc); 307 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 308 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 309 defined(CONFIG_CPU_SUBTYPE_SH7709) 310 plat_irq_setup_sh3(); 311 #endif 312 } 313