1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
261a6976bSPaul Mundt #include <linux/serial_sci.h>
361a6976bSPaul Mundt #include <linux/serial_core.h>
461a6976bSPaul Mundt #include <linux/io.h>
561a6976bSPaul Mundt #include <cpu/serial.h>
664941d89SPaul Mundt #include <cpu/gpio.h>
761a6976bSPaul Mundt 
sh7720_sci_init_pins(struct uart_port * port,unsigned int cflag)861a6976bSPaul Mundt static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
961a6976bSPaul Mundt {
1061a6976bSPaul Mundt 	unsigned short data;
1161a6976bSPaul Mundt 
1261a6976bSPaul Mundt 	if (cflag & CRTSCTS) {
1361a6976bSPaul Mundt 		/* enable RTS/CTS */
1461a6976bSPaul Mundt 		if (port->mapbase == 0xa4430000) { /* SCIF0 */
1561a6976bSPaul Mundt 			/* Clear PTCR bit 9-2; enable all scif pins but sck */
1661a6976bSPaul Mundt 			data = __raw_readw(PORT_PTCR);
1761a6976bSPaul Mundt 			__raw_writew((data & 0xfc03), PORT_PTCR);
1861a6976bSPaul Mundt 		} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
1961a6976bSPaul Mundt 			/* Clear PVCR bit 9-2 */
2061a6976bSPaul Mundt 			data = __raw_readw(PORT_PVCR);
2161a6976bSPaul Mundt 			__raw_writew((data & 0xfc03), PORT_PVCR);
2261a6976bSPaul Mundt 		}
2361a6976bSPaul Mundt 	} else {
2461a6976bSPaul Mundt 		if (port->mapbase == 0xa4430000) { /* SCIF0 */
2561a6976bSPaul Mundt 			/* Clear PTCR bit 5-2; enable only tx and rx  */
2661a6976bSPaul Mundt 			data = __raw_readw(PORT_PTCR);
2761a6976bSPaul Mundt 			__raw_writew((data & 0xffc3), PORT_PTCR);
2861a6976bSPaul Mundt 		} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
2961a6976bSPaul Mundt 			/* Clear PVCR bit 5-2 */
3061a6976bSPaul Mundt 			data = __raw_readw(PORT_PVCR);
3161a6976bSPaul Mundt 			__raw_writew((data & 0xffc3), PORT_PVCR);
3261a6976bSPaul Mundt 		}
3361a6976bSPaul Mundt 	}
3461a6976bSPaul Mundt }
3561a6976bSPaul Mundt 
3661a6976bSPaul Mundt struct plat_sci_port_ops sh7720_sci_port_ops = {
3761a6976bSPaul Mundt 	.init_pins	= sh7720_sci_init_pins,
3861a6976bSPaul Mundt };
39