1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7269 Setup 4 * 5 * Copyright (C) 2012 Renesas Electronics Europe Ltd 6 * Copyright (C) 2012 Phil Edworthy 7 */ 8 #include <linux/platform_device.h> 9 #include <linux/init.h> 10 #include <linux/serial.h> 11 #include <linux/serial_sci.h> 12 #include <linux/usb/r8a66597.h> 13 #include <linux/sh_timer.h> 14 #include <linux/io.h> 15 16 enum { 17 UNUSED = 0, 18 19 /* interrupt sources */ 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 22 23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 24 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15, 25 USB, VDC4, CMT0, CMT1, BSC, WDT, 26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 27 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V, 28 PWMT1, PWMT2, ADC_ADI, 29 SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5, 30 RSPDIF, 31 IIC30, IIC31, IIC32, IIC33, 32 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 33 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, 34 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 35 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, 36 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, 37 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, 38 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, 39 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, 40 RCAN0, RCAN1, RCAN2, 41 RSPIC0, RSPIC1, 42 IEBC, CD_ROMD, 43 NFMC, 44 SDHI0, SDHI1, 45 RTC, 46 SRCC0, SRCC1, SRCC2, 47 48 /* interrupt groups */ 49 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, 50 }; 51 52 static struct intc_vect vectors[] __initdata = { 53 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 54 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 55 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 56 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 57 58 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 59 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 60 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 61 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 62 63 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 64 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 65 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 66 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 67 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 68 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 69 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 70 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 71 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141), 72 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145), 73 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149), 74 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153), 75 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157), 76 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161), 77 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165), 78 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169), 79 80 INTC_IRQ(USB, 170), 81 82 INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172), 83 INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174), 84 INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176), 85 INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177), 86 87 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189), 88 89 INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191), 90 91 INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193), 92 INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195), 93 INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197), 94 INTC_IRQ(MTU0_VEF, 198), 95 INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200), 96 INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202), 97 INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204), 98 INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206), 99 INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208), 100 INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210), 101 INTC_IRQ(MTU3_TCI3V, 211), 102 INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213), 103 INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215), 104 INTC_IRQ(MTU4_TCI4V, 216), 105 106 INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218), 107 108 INTC_IRQ(ADC_ADI, 223), 109 110 INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225), 111 INTC_IRQ(SSIF0, 226), 112 INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228), 113 INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230), 114 INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232), 115 INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234), 116 INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236), 117 118 INTC_IRQ(RSPDIF, 237), 119 120 INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239), 121 INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241), 122 INTC_IRQ(IIC30, 242), 123 INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244), 124 INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246), 125 INTC_IRQ(IIC31, 247), 126 INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249), 127 INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251), 128 INTC_IRQ(IIC32, 252), 129 INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254), 130 INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256), 131 INTC_IRQ(IIC33, 257), 132 133 INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259), 134 INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261), 135 INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263), 136 INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265), 137 INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267), 138 INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269), 139 INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271), 140 INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273), 141 INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275), 142 INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277), 143 INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279), 144 INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281), 145 INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283), 146 INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285), 147 INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287), 148 INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289), 149 150 INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292), 151 INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294), 152 INTC_IRQ(RCAN0, 295), 153 INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297), 154 INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299), 155 INTC_IRQ(RCAN1, 300), 156 INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302), 157 INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304), 158 INTC_IRQ(RCAN2, 305), 159 160 INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307), 161 INTC_IRQ(RSPIC0, 308), 162 INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310), 163 INTC_IRQ(RSPIC1, 311), 164 165 INTC_IRQ(IEBC, 318), 166 167 INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320), 168 INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322), 169 INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324), 170 171 INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326), 172 INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328), 173 174 INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333), 175 INTC_IRQ(SDHI0, 334), 176 INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336), 177 INTC_IRQ(SDHI1, 337), 178 179 INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339), 180 INTC_IRQ(RTC, 340), 181 182 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342), 183 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344), 184 INTC_IRQ(SRCC0, 345), 185 INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347), 186 INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349), 187 INTC_IRQ(SRCC1, 350), 188 INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352), 189 INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354), 190 INTC_IRQ(SRCC2, 355), 191 }; 192 193 static struct intc_group groups[] __initdata = { 194 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 195 PINT4, PINT5, PINT6, PINT7), 196 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), 197 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), 198 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), 199 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), 200 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), 201 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), 202 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), 203 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), 204 }; 205 206 static struct intc_prio_reg prio_registers[] __initdata = { 207 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 208 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 209 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 210 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 211 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 212 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9, 213 DMAC10, DMAC11 } }, 214 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13, 215 DMAC14, DMAC15 } }, 216 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } }, 217 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } }, 218 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } }, 219 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF, 220 MTU1_AB, MTU1_VU } }, 221 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU, 222 MTU3_ABCD, MTU3_TCI3V } }, 223 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V, 224 PWMT1, PWMT2 } }, 225 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } }, 226 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } }, 227 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} }, 228 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } }, 229 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, 230 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } }, 231 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } }, 232 { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } }, 233 { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } }, 234 { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } }, 235 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } }, 236 }; 237 238 static struct intc_mask_reg mask_registers[] __initdata = { 239 { 0xfffe0808, 0, 16, /* PINTER */ 240 { 0, 0, 0, 0, 0, 0, 0, 0, 241 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 242 }; 243 244 static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, 245 mask_registers, prio_registers, NULL); 246 247 static struct plat_sci_port scif0_platform_data = { 248 .scscr = SCSCR_REIE, 249 .type = PORT_SCIF, 250 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 251 }; 252 253 static struct resource scif0_resources[] = { 254 DEFINE_RES_MEM(0xe8007000, 0x100), 255 DEFINE_RES_IRQ(259), 256 DEFINE_RES_IRQ(260), 257 DEFINE_RES_IRQ(261), 258 DEFINE_RES_IRQ(258), 259 }; 260 261 static struct platform_device scif0_device = { 262 .name = "sh-sci", 263 .id = 0, 264 .resource = scif0_resources, 265 .num_resources = ARRAY_SIZE(scif0_resources), 266 .dev = { 267 .platform_data = &scif0_platform_data, 268 }, 269 }; 270 271 static struct plat_sci_port scif1_platform_data = { 272 .scscr = SCSCR_REIE, 273 .type = PORT_SCIF, 274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 275 }; 276 277 static struct resource scif1_resources[] = { 278 DEFINE_RES_MEM(0xe8007800, 0x100), 279 DEFINE_RES_IRQ(263), 280 DEFINE_RES_IRQ(264), 281 DEFINE_RES_IRQ(265), 282 DEFINE_RES_IRQ(262), 283 }; 284 285 static struct platform_device scif1_device = { 286 .name = "sh-sci", 287 .id = 1, 288 .resource = scif1_resources, 289 .num_resources = ARRAY_SIZE(scif1_resources), 290 .dev = { 291 .platform_data = &scif1_platform_data, 292 }, 293 }; 294 295 static struct plat_sci_port scif2_platform_data = { 296 .scscr = SCSCR_REIE, 297 .type = PORT_SCIF, 298 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 299 }; 300 301 static struct resource scif2_resources[] = { 302 DEFINE_RES_MEM(0xe8008000, 0x100), 303 DEFINE_RES_IRQ(267), 304 DEFINE_RES_IRQ(268), 305 DEFINE_RES_IRQ(269), 306 DEFINE_RES_IRQ(266), 307 }; 308 309 static struct platform_device scif2_device = { 310 .name = "sh-sci", 311 .id = 2, 312 .resource = scif2_resources, 313 .num_resources = ARRAY_SIZE(scif2_resources), 314 .dev = { 315 .platform_data = &scif2_platform_data, 316 }, 317 }; 318 319 static struct plat_sci_port scif3_platform_data = { 320 .scscr = SCSCR_REIE, 321 .type = PORT_SCIF, 322 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 323 }; 324 325 static struct resource scif3_resources[] = { 326 DEFINE_RES_MEM(0xe8008800, 0x100), 327 DEFINE_RES_IRQ(271), 328 DEFINE_RES_IRQ(272), 329 DEFINE_RES_IRQ(273), 330 DEFINE_RES_IRQ(270), 331 }; 332 333 static struct platform_device scif3_device = { 334 .name = "sh-sci", 335 .id = 3, 336 .resource = scif3_resources, 337 .num_resources = ARRAY_SIZE(scif3_resources), 338 .dev = { 339 .platform_data = &scif3_platform_data, 340 }, 341 }; 342 343 static struct plat_sci_port scif4_platform_data = { 344 .scscr = SCSCR_REIE, 345 .type = PORT_SCIF, 346 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 347 }; 348 349 static struct resource scif4_resources[] = { 350 DEFINE_RES_MEM(0xe8009000, 0x100), 351 DEFINE_RES_IRQ(275), 352 DEFINE_RES_IRQ(276), 353 DEFINE_RES_IRQ(277), 354 DEFINE_RES_IRQ(274), 355 }; 356 357 static struct platform_device scif4_device = { 358 .name = "sh-sci", 359 .id = 4, 360 .resource = scif4_resources, 361 .num_resources = ARRAY_SIZE(scif4_resources), 362 .dev = { 363 .platform_data = &scif4_platform_data, 364 }, 365 }; 366 367 static struct plat_sci_port scif5_platform_data = { 368 .scscr = SCSCR_REIE, 369 .type = PORT_SCIF, 370 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 371 }; 372 373 static struct resource scif5_resources[] = { 374 DEFINE_RES_MEM(0xe8009800, 0x100), 375 DEFINE_RES_IRQ(279), 376 DEFINE_RES_IRQ(280), 377 DEFINE_RES_IRQ(281), 378 DEFINE_RES_IRQ(278), 379 }; 380 381 static struct platform_device scif5_device = { 382 .name = "sh-sci", 383 .id = 5, 384 .resource = scif5_resources, 385 .num_resources = ARRAY_SIZE(scif5_resources), 386 .dev = { 387 .platform_data = &scif5_platform_data, 388 }, 389 }; 390 391 static struct plat_sci_port scif6_platform_data = { 392 .scscr = SCSCR_REIE, 393 .type = PORT_SCIF, 394 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 395 }; 396 397 static struct resource scif6_resources[] = { 398 DEFINE_RES_MEM(0xe800a000, 0x100), 399 DEFINE_RES_IRQ(283), 400 DEFINE_RES_IRQ(284), 401 DEFINE_RES_IRQ(285), 402 DEFINE_RES_IRQ(282), 403 }; 404 405 static struct platform_device scif6_device = { 406 .name = "sh-sci", 407 .id = 6, 408 .resource = scif6_resources, 409 .num_resources = ARRAY_SIZE(scif6_resources), 410 .dev = { 411 .platform_data = &scif6_platform_data, 412 }, 413 }; 414 415 static struct plat_sci_port scif7_platform_data = { 416 .scscr = SCSCR_REIE, 417 .type = PORT_SCIF, 418 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 419 }; 420 421 static struct resource scif7_resources[] = { 422 DEFINE_RES_MEM(0xe800a800, 0x100), 423 DEFINE_RES_IRQ(287), 424 DEFINE_RES_IRQ(288), 425 DEFINE_RES_IRQ(289), 426 DEFINE_RES_IRQ(286), 427 }; 428 429 static struct platform_device scif7_device = { 430 .name = "sh-sci", 431 .id = 7, 432 .resource = scif7_resources, 433 .num_resources = ARRAY_SIZE(scif7_resources), 434 .dev = { 435 .platform_data = &scif7_platform_data, 436 }, 437 }; 438 439 static struct sh_timer_config cmt_platform_data = { 440 .channels_mask = 3, 441 }; 442 443 static struct resource cmt_resources[] = { 444 DEFINE_RES_MEM(0xfffec000, 0x10), 445 DEFINE_RES_IRQ(188), 446 DEFINE_RES_IRQ(189), 447 }; 448 449 static struct platform_device cmt_device = { 450 .name = "sh-cmt-16", 451 .id = 0, 452 .dev = { 453 .platform_data = &cmt_platform_data, 454 }, 455 .resource = cmt_resources, 456 .num_resources = ARRAY_SIZE(cmt_resources), 457 }; 458 459 static struct resource mtu2_resources[] = { 460 DEFINE_RES_MEM(0xfffe4000, 0x400), 461 DEFINE_RES_IRQ_NAMED(192, "tgi0a"), 462 DEFINE_RES_IRQ_NAMED(203, "tgi1a"), 463 }; 464 465 static struct platform_device mtu2_device = { 466 .name = "sh-mtu2", 467 .id = -1, 468 .resource = mtu2_resources, 469 .num_resources = ARRAY_SIZE(mtu2_resources), 470 }; 471 472 static struct resource rtc_resources[] = { 473 [0] = { 474 .start = 0xfffe6000, 475 .end = 0xfffe6000 + 0x30 - 1, 476 .flags = IORESOURCE_IO, 477 }, 478 [1] = { 479 /* Shared Period/Carry/Alarm IRQ */ 480 .start = 338, 481 .flags = IORESOURCE_IRQ, 482 }, 483 }; 484 485 static struct platform_device rtc_device = { 486 .name = "sh-rtc", 487 .id = -1, 488 .num_resources = ARRAY_SIZE(rtc_resources), 489 .resource = rtc_resources, 490 }; 491 492 /* USB Host */ 493 static struct r8a66597_platdata r8a66597_data = { 494 .on_chip = 1, 495 .endian = 1, 496 }; 497 498 static struct resource r8a66597_usb_host_resources[] = { 499 [0] = { 500 .start = 0xe8010000, 501 .end = 0xe80100e4, 502 .flags = IORESOURCE_MEM, 503 }, 504 [1] = { 505 .start = 170, 506 .end = 170, 507 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 508 }, 509 }; 510 511 static struct platform_device r8a66597_usb_host_device = { 512 .name = "r8a66597_hcd", 513 .id = 0, 514 .dev = { 515 .dma_mask = NULL, /* not use dma */ 516 .coherent_dma_mask = 0xffffffff, 517 .platform_data = &r8a66597_data, 518 }, 519 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), 520 .resource = r8a66597_usb_host_resources, 521 }; 522 523 static struct platform_device *sh7269_devices[] __initdata = { 524 &scif0_device, 525 &scif1_device, 526 &scif2_device, 527 &scif3_device, 528 &scif4_device, 529 &scif5_device, 530 &scif6_device, 531 &scif7_device, 532 &cmt_device, 533 &mtu2_device, 534 &rtc_device, 535 &r8a66597_usb_host_device, 536 }; 537 538 static int __init sh7269_devices_setup(void) 539 { 540 return platform_add_devices(sh7269_devices, 541 ARRAY_SIZE(sh7269_devices)); 542 } 543 arch_initcall(sh7269_devices_setup); 544 545 void __init plat_irq_setup(void) 546 { 547 register_intc_controller(&intc_desc); 548 } 549 550 static struct platform_device *sh7269_early_devices[] __initdata = { 551 &scif0_device, 552 &scif1_device, 553 &scif2_device, 554 &scif3_device, 555 &scif4_device, 556 &scif5_device, 557 &scif6_device, 558 &scif7_device, 559 &cmt_device, 560 &mtu2_device, 561 }; 562 563 void __init plat_early_device_setup(void) 564 { 565 early_platform_add_devices(sh7269_early_devices, 566 ARRAY_SIZE(sh7269_early_devices)); 567 } 568